ADP1071-1 : Start Up Behavior

I'm designing in ADP1071-1 PWM controller to regulate a two-switch flyback auxiliary power converter. As I'm going through the design I've encountered a few gray areas I was hoping to gain some insight on.

  1. The "GATE PIN" of the ADP1071-1 in my design is driving two inputs to a high side/low side driver which is high impedance input, I'm not utilizing the 1A driving capability of the PWM controller as the FETs are being driven by a dual driver external to the IC. How is this going to effect the "open loop slow start" I can still insert two gate resistors from GATE to GND for "Start-up", but does the equivalent resistance need to be exactly 10k, 22k, 47k, 100k or is it alright to be somewhere in between? Does the fact that I no longer have a low impedance path (capacitive-gate of MOSFET) influence the open loop slow start behavior?
  2. Could you provide some guideline as to sizing the capacitor on the secondary side soft-start PIN? Maybe in relation to the "open loop" soft-start before it takes over to achive a similar slope of Vout? I see the current source and can size the capacitor to achieve a certain time constant, but not sure what time constant makes sense.
  3. In order to complete the "Closed Loop" small signal analysis I generally need to know 3 parameters, Se, Sn and Gfb which translate to the slope of the slope compensator, slope of the sensed voltage and the small signal gain(mid-band gain) of the voltage feedback loop. I can calculate Se and Sn based on data provided in the datasheet, but not sure what Gfb is? I see a value of k = 0.5 and I think that may be it, but would you confirm? Or is the k=0 associated with the gain of the primary current sense signal?
  4. Are you planning on releasing an LTSpice simulation model for ADP1071-1/2 anytime soon? I know this question is already on the forum, but I'm wondering if someone is already working on it or is still undecided if generating a spice model is part of the scope.

Thank you!

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  • 0
    •  Analog Employees 
    on Oct 11, 2018 7:02 PM

    Hi azlatev,

    Your answers are below:

    1.  Typically the values have to be close to the recommended values. It's ok to be somewhere in between so you get something that is not what you want, you can always adjust it. Typically a 10k resistor works well.

    2. For SS2 cap, typically 0.1uF will give you b/w 5-10ms of softstart time depending on the load. A more conservative cap is 0.47uF which should be suficient for most cases.

    3. Are you referring to the transconductance of the gm amplifier when you mean Gfb? It is 250 uA/V.

    4. Yes, there shoud be a model coming soon but I can't clearly say when. 

    Please feel free to post other questions if you need more answers.

    Lt Comm Data.

  • Thank you for the quick response, it's very much appreciated! I have accounted for the gain of the transconductance amp. There are two paths prior to the comparator stage which attribute to the low frequency gain, one is the sensed primary current generating a ramp and the other is from the voltage feedback loop, I have outlined the two in the attachment. The voltage feedback loop shows blocks "Tx",feedback isolation transformer, "COMP" and "Primary to Secondary Handover Logic" in the feedback path, can I assume a unity low frequency gain past the transconductance amplifier stage?

    On a separate note, I took a look at the reference design for ADP1071-1 today and was mildly disappointed to see the switching frequency set to 50kHz, close loop bandwidth merely 400Hz and not utilizing the "free" synchronous rectification. I would imagine if you wanted to show the full potential of the part you would aim for a design switching at 400-500kHz, with closed loop bandwidth in the range of 2-3kHz(to show the superiority of an icoupler vs a traditional opto-isolation) and utilize the secondary synchronous rectifier drive. Is there are reason you wouldn't recommend using the synchronous rectifier drive on one output(the heaviest loaded one) on a converter with multiple secondaries and use diode rectification on the lower loaded windings?

      Scanned from ORCAS.pdf

Reply
  • Thank you for the quick response, it's very much appreciated! I have accounted for the gain of the transconductance amp. There are two paths prior to the comparator stage which attribute to the low frequency gain, one is the sensed primary current generating a ramp and the other is from the voltage feedback loop, I have outlined the two in the attachment. The voltage feedback loop shows blocks "Tx",feedback isolation transformer, "COMP" and "Primary to Secondary Handover Logic" in the feedback path, can I assume a unity low frequency gain past the transconductance amplifier stage?

    On a separate note, I took a look at the reference design for ADP1071-1 today and was mildly disappointed to see the switching frequency set to 50kHz, close loop bandwidth merely 400Hz and not utilizing the "free" synchronous rectification. I would imagine if you wanted to show the full potential of the part you would aim for a design switching at 400-500kHz, with closed loop bandwidth in the range of 2-3kHz(to show the superiority of an icoupler vs a traditional opto-isolation) and utilize the secondary synchronous rectifier drive. Is there are reason you wouldn't recommend using the synchronous rectifier drive on one output(the heaviest loaded one) on a converter with multiple secondaries and use diode rectification on the lower loaded windings?

      Scanned from ORCAS.pdf

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