I am working on a design that uses the LTC4364 to clamp transients of up to 60V down to 40V. A 10uF (+-10%) timer cap is used, for a timeout period of 1.06s.Itmrup,OV = 2uA + .644uA/V * (60V - 40V - .5) = 14.56uA
tOV = 10uF*1.25V/14.56uA + 10uF*100mV/5uA = 1.06s
The LTSpice sim results match the calculations, but measurements from actual boards have a timeout of 1.84-1.9s.
The increased time is not a problem, it is still well within the SOA of M1, but if the time decreases by a similar amount on future boards, it will fail tests requiring it to continue operation during transients. Can this large of a difference be a part tolerance issue, or is there something else I should be looking at?
(I can make an edited schematic and post it as well if that would be helpful)