I read some answers such as "since ADP1047 is designed for PFC, its loop bandwidth is slow".
This is how the traditional boost circuits work.
But why would you predestine a whole new part for such a narrow application?
This slow BW comes from the fact that the output of ALL 60 Hz single phase has awful line harmonics. Even gazzillion mF wont kill that . BUT there are new topologies that do not have this limitation.
So then how can I modify this predestined limitation?
What is the way to design loop BW according to the power stage? Through the GUI?
BTW: can multiple ADP1047 chips be synchronized? How?