I read some answers such as "since ADP1047 is designed for PFC, its loop bandwidth is slow".
This is how the traditional boost circuits work.
But why would you predestine a whole new part for such a narrow application?
This slow BW comes from the fact that the output of ALL 60 Hz single phase has awful line harmonics. Even gazzillion mF wont kill that . BUT there are new topologies that do not have this limitation.
So then how can I modify this predestined limitation?
What is the way to design loop BW according to the power stage? Through the GUI?
BTW: can multiple ADP1047 chips be synchronized? How?
The ADP1047/8 was released in 2012 and is for single phase, interleaved and bridgless boost PFCs.
Can you please give me an example where you want a very fast voltage loop? You can increase the bandwidth of the voltage loop as much as you like but there is a limitation in the current filter design that does not allow you to place the zero beyond 50Hz.
To answer your other questions:
1. Yes, the filter settings are programmed through the GUI
2. For SYNC, it is possible to SYNCronize 2 ADP1047/8 together using the SYNC pin.
Lt. Comm. Data.
For example, in radar transmitter applications where the converter will only provide peak currents. It is essential the droop during the widely varying pulse widths be less than a specified amount. This cannot be defeated by using lots of capacitors. To handle this situation, we have developed a unique approach in which none of the truism about 60Hz single phase boost stage is applicable. Furthermore, all aerospace applications we deal with require extremely low ripple due to huge pulse currents all the while maintaining high efficiency. Requirements are almost as one finds in VRMs but at high voltages with much higher currents. There are lots of control schemes we employ but some of them are not applicable. Finally, a second stage of buck can be used but it kills "size, weight, adoptive and power(SWAP") attributes.
Another example will be a new version of "tracking power supply". But not at all the way LTE or cell phone industry was required to do. But the requirement to change the output voltage rapidly is a highly desired. I think our one stage approach will deliver it provided we use digital control similar to ADP1047 but modified.
In fact in our power stage, we do not strictly need a current sensing to shape the current at all. Yet we spent several months trying to "synthesize" the current that the analog cousin of the PFC process ADP1047 uses( eg. LT1508) to no avail. The issue of high power dissipation in Rs is also a problem. But not knowing the full story of the control in ADP1047, we struggled to maintain current sensing- not necessarily to shape it.
This is another topic we would very much like to explore with you. Synthesized return current without Rs! Which relates to the gain used in the algorithm.
LtComm, when you use the words " there is a limitation in the current filter design" you mean existing outer loop filter design or referring to sensing current & its associated filter zero? I believe it is the former.
Why 50 Hz?...... I can send you a phase portrait of our power stage: it is vastly different from non-minimal phase boost stage which seems to be the basis of the limitation.
In aerospace, line frequency is 400 Hz. & as I mentioned, in our output there is no spectral component of 400 Hz or any of its harmonics. In theory, output ripple is "0"
Can we meet to discuss further this matter of control adaptation to this unique power stage? A lot of this is proprietary so cannot be disclosed publicly yet. But we do have an NDA with ADI.
We are a bit concerned at this time because field guys told us the source code cannot be released for adaptation. As in TI’s solution for UCD3138- it is there for download for free & you cook it up the way you want.
But this is fine: will you find people in ADI to do it for us?...meanwhile, I am sitting on the whole $1000 eval kit....unopened.
Appreciate your prompt response, Sir!
Hope to get to the bottom of it all soon.
LTComm: I got a reply saying that after review they think the questions should go to Linear Tech. But my issues span both LT1509 & ADP 1047.
Pl take note of that.
LT: I will have 18 ADP1047/48 running in this system. How would I to synchronize these in the following manner
- 6 of these in same phase
- 6 of the next set out of phase by 120 deg
-rest out of phase by 240
There used to be a chip that gave out of phase signals ....but just cannot retrieve it by searching. Is that chip taken out of parts made by ADI/LT?
Of course, question remains how to do it in circuit.
Please see the GUI PWM settings to SYNC several ADP1048s with appropriate phase delay. Also see attached. Essentially, you send the same SYNC pulse to all the ADP1048s and in the GUI you can set the phase delay.
From what you are describing what you need is just a simple boost converter and the ADP1048 is a power factor controller and hence the poles and zeros are so low as you have found them in the controller. Seems like you are more interested in output ripple cancellation than reducing THD. Do you need power factor correction? What is the total output wattage? Also, what is the reason for putting 18 in parallel?