About LTM8057

I am considering a circuit with 12V input / 10.6V output using LTM8057.

About simulation with LTspice

A 3.57kΩ resistor and an 8.2pF capacitor are connected to the ADJ terminal.
When connecting Load Resistance 430Ω to Vout and performing simulation with LTspice, output becomes 12V, why?
We believe that it also meets minimum load capacity.

If a capacitor is connected to the ADJ terminal, the output voltage may not be stable due to the simulation result,
Is it better not to connect capacitors in simulation?



Add image (LTspice)
[edited by: Naoki at 1:40 AM (GMT -4) on 29 Aug 2018]
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  • +1
    •  Analog Employees 
    on Sep 11, 2018 5:10 PM

    Hi

    The regulation issue at light load is related to parasitic circuit impedances that cause ringing in the feedback sense circuit, and are not accurately modeled in LTspice. The datasheet recommendations are based on measurement of the actual circuit. I believe that not adding capacitance to ADJ in the LTspice simulation will yield better results.

Reply
  • +1
    •  Analog Employees 
    on Sep 11, 2018 5:10 PM

    Hi

    The regulation issue at light load is related to parasitic circuit impedances that cause ringing in the feedback sense circuit, and are not accurately modeled in LTspice. The datasheet recommendations are based on measurement of the actual circuit. I believe that not adding capacitance to ADJ in the LTspice simulation will yield better results.

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