After a redesign there are problems with the ADP5135. The output voltage is at 3.8V with 0.5A to 1A load. The output voltage is constant at 3.8V. But the signal at SW3 hat an irregular on-/off-time. See attached picture.
Has anyone an idea where the problems are?
BTW: PWM/PSM is active
The main problem is when I drive a temperature profile there is ripple of about 40kHz at the output signal. This frequency is present at our RF output signal as a spur 40kHz beside the CW signal.
I think that this is in relation with the irregular on-/off-time. The irregular on-/off-time is present all time also at room temperature.
The loads are 2 clock buffer and 2 RF transceiver modules. When I support the clock buffer with an external voltage supply, the spur is still there. But if I supply the RF modules external, it vanished. The RF modules did not change during redesign.
The resistors of the voltage divider are 10k and 64k9. So the voltage is 3.745V. The capacitive load is 100uF per RF module and 10uF at the ADP5135.
During redesign there were no changes at the parts. Only the layout changed.
I did not use ADISimPower for the design.
I have check the following points:
1.) Added a 1nF capacitor between Vout3 and FB3 -> this changed the ripple frequency to 200kHz. On-/off-time at RT is constant and irregular at low temperature
2.) Used a 1nF capacitor between FB3 and GND -> no chnages
3.) Used a 10nF capacitor between FB3 and GND -> going instable
4.) Set Mode pin to 3V. Always at PWM mode. -> no changes
5.) added 22uF capacitor in parallel to Cout -> no changes
6.) added 1uF capacitor in parallel to Cout -> no changes
Do you have any other ideas?
At 0.5 to 1A load, the part will switch in PWM mode even if you tie the Mode pin low. How does the layout of the feedback loop of Buck3 looks like? You'd want to keep that away from any of the SW nodes, or any other noisy sections in your board to prevent noise coupling into the FB pin.
I suggest you also look at the inductor current, VIN and VOUT(AC coupled), and also the current downstream. It looks like the output voltage is being pulled down in some cycles, hence the part needs to switch ON longer to bring it back up. If you don't mind sharing your schematic, that would help too.
Here are the old and the new layout.
And the schematic.
Are there any solutions?
Looking at the top layer, I can't seem to spot any changes between the two layouts.
Were you able to capture the other signals?