we have a problem with a LTC4011 based NiMH charger design:
The LTC4011 seems to be very sensitivy on slight spikes / voltage changes happening on its "DCIN" Pin side. Then the LTC4011 resets itself and begins a new charging cycle.
We are using pretty much the reference circuit design shown below:
We stabilized the VCC side with 10uF and also the DCIN side with 10uF (and other C combinationswere tested). It helped to become more stable but it´s still quite sensitive.
The datasheets shows curves of the allowed voltage difference between DCIN and VCC Pin being around +/- 30mV.
How can the two voltages be stabilized enough to not go into the shutdown ? Could not find information about C´s or layout consideration when having a little noise environment.
Thank you very much
Little Bug with pictures included, used reference design is:
If you are hitting the threshold voltage, there are a few things you can do to improve that:
1. Perhaps your INFET FET needs to have less Rds(on). What is the FET model?
2. Operate with DCIN higher with reference to your battery voltage.
Do you have a scope plot of this happening? I'd like to see how fast it is.
thanks for your reply.
PMOS was already in Focus: Our problem occurs while Battery is not charged, so no serious current flows through the PMOS. In this case, we measured ~60mV drop over the PMOS. We compared it to the 4011 Eval Board, there the PMOS has ~50mV drop.
I´m currently not in Office so I can not provide the PMOS type we used.
What I dont understand: We replaced the PMOS for testing with a diode. The diode has ~200mV Voltage drop. The resetting behaviour is more or less the same. When the threshold is areound 30mV, why can the LTC4011 operate with a diode with such a high voltage drop ?
To your 2. point: how can DCIN be higher than VCC ? Our DCIN is 12V, Battery has ~7V...
It would be good to capture the spikes that are causing this - a scope plot of DCIN goind below VCC during operation. If your DCIN dips ~25mV below VCC then this can happen. The solution here is to mitigate these spikes so this does not happen. More capacitance may fix it.
Regarding point 2, DCIN is higher than VCC when current flows from DCIN to VCC due to the resistance of the FET.