Hi,
I am working on a project implementing the LTC2949. I've noticed a number of discrepancies in the datasheet specifically regarding byte ordering:
ltc2949.pdf, Rev A:
1. PEC appears reversed
(Page 33, table 11): For each of the frame layout tables in the datasheet, such as this one, the PEC appears with the lowest byte first in the order, followed by the highest byte. The only way to get the LTC2949 to respond to a DCMD read is with the PEC reversed so that it is represented as big endian. This is further confused by the unlabeled table on page 31 showing example transactions with the LTC2949. In the example for CONT0 at least, the PEC is actually shown as big endian. I think it must be the case that the chip is actually designed to transact PEC as big endian. I am computing PEC via the given example code on page 40.
2. Little endian blurb is wrong
(Page 42, "MEMORY MAP AND PAGING MECHANISM") Has the following blurb:
Multiple-byte data is stored with most significant byte at the lowest address (little-endian). For instance, the MSB C1[47:40] of the quantity C1 is stored at address 0x00 in PAGE0.
This blurb is incorrect. Little endian is the opposite of this statement. This is further confused by the following statement:
Note that reading data from LTC2949's memory map (no matter if using direct command or indirect memory access RDCV command with RDCVCONF=0) reports MSBytes first,
So if reading data out, do we really get the least significant byte or the actual value first since it's stored as big endian?
Would it be possible for an LT engineer to review/fix this datasheet? These are fundamental problems that make implementing this part a lot more frustrating than it should ever be.
