Purpose and placement of external clamp network (BAV70 / SMBJ75A-13) in N-MOSFET passive balancing implementation

EHR said:

1. External clamp usage
   In the ADBMS6830B datasheet I do not see an explicit requirement to use external clamp devices such as BAV70 or SMBJ75A-13 on the S pins or balancing network.
   The datasheet mentions that the IC is hot plug tolerant without external protection, and it also shows internal protection structures in the internal protection section.
   Because of this, I am not sure in which situations these external clamp components are actually required, recommended, or optional.
2. Why are these clamp components only used from around Cell 7 upward in the evaluation board
   In the EVAL-ADBMS6830BMSW schematic, the BAV70 clamp network appears only on the upper channels, and there is also an SMBJ75A-13 on the clamp rail.
   I do not understand why this is only implemented from approximately Cell 7 and above, instead of on every balancing channel.

Is this related to the absolute voltage potential of the upper cells with respect to V minus?
In other words, is the reason that from Cell 7 upward the common-mode voltage becomes high enough that additional external clamping is useful or necessary, while for the lower cells it is not?

These diodes are for surge protection. Surge transients generated during bus bar connection, DC fast charging, or inverter spikes in the system with ADBMS6830B. To prevent current from flowing into the internal protection circuit from these surge event and damaging IC channels we have this BAV70 +SMB diodes installed. 
The diodes are attached to higher channels only since they are the ones with highest potential (and hence highest current flow) and if we can clamp those voltages down to a safe level below abs max the part will be able to survive. Normally when there is a surge, they get divided among all channels but since higher channels are already at a higher potential, the voltage (and current flowing) there gets comparably bigger than the lower channel. This is the reason why we add them to the higher channels from S8 to top channel. SMBJ75A is added so that there won't always be leakage through the diodes attached to the S-Channels (since they are forward biased) which will cause measurement errors, and this diode will only get activated when there is a surge transient above 121V.

The green marked voltages are voltage of that node when surge happens; RED is the current flowing at each node. As you can see the highest channel has the highest current flow, then the second biggest is the channel below that, and so on.S8 is when the current is low enough that it will not damage the internal structure even in the vent of surge.

EHR said:

Are these parts intended mainly for ESD, transient suppression, hot-plug stress, balancing switch protection, or some other specific condition?

These are mainly for transient suppression as mentioned above. You can use any part similar to BAV70 for this purpose.

EHR said:

For our design, we are implementing passive balancing with external N-channel MOSFETs, following the concept shown in Figure 40 of the datasheet.
Because I did not fully understand the reason for placing the clamp only on the upper channels in the eval board, I initially added the clamp network on every SxP and SxN pair in our redesign.

For FSAE designs external balancing is not really necessary, but if you need more than 300mA of balancing current you can design external balancing circuit. Your circuit can have the footprint for all the clamps and later during testing if you observe damages due to surge you can start populating them later. You r circuit here makes sense, there might be small leakage due to the TVS at higher temperatures but even then it will not cause any major error in measurement. 

EHR said:

3. Difference between datasheet figures and eval board values
   I also noticed that the component values used in the eval board differ significantly from the values shown in the datasheet figures:

• In the functional block diagram, the balancing-related resistors are shown as 10 ohm and the capacitor as 100 nF.
• In the evaluation board schematic, I see 15 ohm resistors and 0.22 uF capacitors in the balancing-related path.
  I understand that the functional block diagram is not necessarily intended as a design-ready application schematic, but I would still appreciate clarification on the practical design guidance here.

The balancing resistor value depends on the balancing current you will need in your system. This value is custom for each user according to the maximum balancing current needed. if you use lower balancing resistor you will have more balancing current for the same battery voltage. the datasheet figure and eval board figures are different because of this reason. 

EHR said:

Since ADI is one of our sponsors, we would like to document this topic properly and avoid any major design mistake before finalizing the new board.
If useful, we can also share our updated schematic by email for review.

If you are an FSAE student, please check your document package from ADI for the email to reach out for support. We have a dedicated team for helping ADI sponsored FSAE student groups. 

EHR said:

1. External clamp usage
   In the ADBMS6830B datasheet I do not see an explicit requirement to use external clamp devices such as BAV70 or SMBJ75A-13 on the S pins or balancing network.
   The datasheet mentions that the IC is hot plug tolerant without external protection, and it also shows internal protection structures in the internal protection section.
   Because of this, I am not sure in which situations these external clamp components are actually required, recommended, or optional.
2. Why are these clamp components only used from around Cell 7 upward in the evaluation board
   In the EVAL-ADBMS6830BMSW schematic, the BAV70 clamp network appears only on the upper channels, and there is also an SMBJ75A-13 on the clamp rail.
   I do not understand why this is only implemented from approximately Cell 7 and above, instead of on every balancing channel.

Is this related to the absolute voltage potential of the upper cells with respect to V minus?
In other words, is the reason that from Cell 7 upward the common-mode voltage becomes high enough that additional external clamping is useful or necessary, while for the lower cells it is not?

These diodes are for surge protection. Surge transients generated during bus bar connection, DC fast charging, or inverter spikes in the system with ADBMS6830B. To prevent current from flowing into the internal protection circuit from these surge event and damaging IC channels we have this BAV70 +SMB diodes installed. 
The diodes are attached to higher channels only since they are the ones with highest potential (and hence highest current flow) and if we can clamp those voltages down to a safe level below abs max the part will be able to survive. Normally when there is a surge, they get divided among all channels but since higher channels are already at a higher potential, the voltage (and current flowing) there gets comparably bigger than the lower channel. This is the reason why we add them to the higher channels from S8 to top channel. SMBJ75A is added so that there won't always be leakage through the diodes attached to the S-Channels (since they are forward biased) which will cause measurement errors, and this diode will only get activated when there is a surge transient above 121V.

The green marked voltages are voltage of that node when surge happens; RED is the current flowing at each node. As you can see the highest channel has the highest current flow, then the second biggest is the channel below that, and so on.S8 is when the current is low enough that it will not damage the internal structure even in the vent of surge.

EHR said:

Are these parts intended mainly for ESD, transient suppression, hot-plug stress, balancing switch protection, or some other specific condition?

These are mainly for transient suppression as mentioned above. You can use any part similar to BAV70 for this purpose.

EHR said:

For our design, we are implementing passive balancing with external N-channel MOSFETs, following the concept shown in Figure 40 of the datasheet.
Because I did not fully understand the reason for placing the clamp only on the upper channels in the eval board, I initially added the clamp network on every SxP and SxN pair in our redesign.

For FSAE designs external balancing is not really necessary, but if you need more than 300mA of balancing current you can design external balancing circuit. Your circuit can have the footprint for all the clamps and later during testing if you observe damages due to surge you can start populating them later. You r circuit here makes sense, there might be small leakage due to the TVS at higher temperatures but even then it will not cause any major error in measurement. 

EHR said:

3. Difference between datasheet figures and eval board values
   I also noticed that the component values used in the eval board differ significantly from the values shown in the datasheet figures:

• In the functional block diagram, the balancing-related resistors are shown as 10 ohm and the capacitor as 100 nF.
• In the evaluation board schematic, I see 15 ohm resistors and 0.22 uF capacitors in the balancing-related path.
  I understand that the functional block diagram is not necessarily intended as a design-ready application schematic, but I would still appreciate clarification on the practical design guidance here.

The balancing resistor value depends on the balancing current you will need in your system. This value is custom for each user according to the maximum balancing current needed. if you use lower balancing resistor you will have more balancing current for the same battery voltage. the datasheet figure and eval board figures are different because of this reason. 

EHR said:

Since ADI is one of our sponsors, we would like to document this topic properly and avoid any major design mistake before finalizing the new board.
If useful, we can also share our updated schematic by email for review.

If you are an FSAE student, please check your document package from ADI for the email to reach out for support. We have a dedicated team for helping ADI sponsored FSAE student groups.