Using Vreg to power galvanically isolated SPI lines with MCU ?

Bird said:

This suggests that the only possible way to use SPI through the galvanic isolator is to provide +5V power from the external source referenced to the same common GND of the LTC board, even if the Vreg is produced on board. And this external +5V should power at least the LTC side of the isolator only... or may be also to power Vreg input pin of LTC6811-1  ?

Your understanding is correct.  A 5V converter would need to be powered from the stack, there is no way to force VREG to stay on forever on LTC6811.  Alternatively an isolated DC/DC converter could be powered from the same source as the MCU, but this is expensive.

Typically SPI is not used with more than one LTC6811 in the system.  To isolate the stack from the microcontroller, LTC6820, ADBMS6821, or ADBMS6822 is used to convert the MCU SPI to isoSPI.  This allows isolation using a simple transformer for isolation between each LTC device rather than complex SPI isolators:

Thank you for this clarification , one question is still unanswered : should the external +5V converter from the stack  power only the LTC side of the galvanic isolator for 4-wire SPI or this power should also go to the Vreg input pin of LTC6811-1 (even though still connected to the on-board NPN transistor emitter) ?

As for the

mvrablic said:

Typically SPI is not used with more than one LTC6811 in the system.

In our current experiment we use 4-wire SPI on the bottom LTC2259A board of the total two-boards stack and this SPI connects to MCU SPI over the galvanic isolator.. This bottom board A port is 4-wire SPI , while B port is isoSPI which connects to the daisy-chained second LTC2259A board.

This is from the LTC6811-1 datasheet (page 46)

The LTC6811-1 has two serial ports which are called Port B
and Port A. Port B is always configured as a 2-wire inter-
face (master). Port A is either a 2-wire or 4-wire interface
(slave), depending on the connection of the ISOMD pin

This is our current configuration, it has a disadvantage as the polling can be done only in one way but in so minimal system this is OK. In our next prototype we'll have more BMS boards so we'll be using LTC6820 chips for dual poll (from the top and bottom).

Again thanks for your reply and waiting for the above clarification.

It is important to clarify this point whether the external +5V power might be applied only to BMS side of the galvanic isolation of 4-wire SPI lines (while Vreg input pin is powered internally as in DC 2259 demo board) or external +5V should also reach the Vreg input pin of LTC6811 ( despite NPN transistor' emitter still connected to it on this board, there is no option to disconnect it in case of internally powered Vreg).

Please clarify.

Bird said:

Thank you for this clarification , one question is still unanswered : should the external +5V converter from the stack  power only the LTC side of the galvanic isolator for 4-wire SPI or this power should also go to the Vreg input pin of LTC6811-1 (even though still connected to the on-board NPN transistor emitter) ?

Either way works, if you use the 5V converter for the VREG then it will save some BOM cost by allowing removal of the NPN for the DRIVE pin.  But ultimately this is quite an uncommon configuration as isoSPI with a normal transformer plus ADBMS6821/22 is cheaper than either of these methods since it avoids the need for a 5V converter and SPI isolator entirely.