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Cell voltages are ~60% of true values, and CRC passes

Category: Hardware
Product Number: LTC6813-1

We have a daisy-chain configuration with two LTC6813 chips, each managing 14 cells. The measured cell voltages from the first chip in the daisy chain look like a normal distribution centered around 2.0V, even though the true values are around 3.5V:

Meanwhile, the 14 cells from the next LTC chip read correctly, as a normal distribution centered at 3.5V:

Sometimes, all the cells voltage reads will be correct (~3.5V), while other times, all of them will be wrong, but still normally distributed around some seemingly arbitrary mean like 2.0V or 2.3V.

I know this isn't some strange bit shift issue because the CRC is passing, so these numbers are truly what the LTC is reporting. I've replicated this issue on multiple boards as well.

I checked the STAT registers, too, and the chip with the strange measurements reports a low analog supply (2.9V) while the good one sees 5.0V. Similar low voltage on the digital supply. We checked REF1 with a multimeter and it appeared to be 5.0V though.

Any idea what could be causing the ADC reads to be incorrect in such a way?

Thanks,

Matthew

  • An incorrect VREF1 could lead to this, VREF1 should not be 5V, its nominal value is ~3.15V.

    The VREF1 pin is no loads allowed and should have a 1uF bypass capacitor to GND.  It should have no other connections besides the bypass capacitor (see DC2350B for reference).

    If this is present, is it possible to share the schematic so we can check for any other issues? 

  • The V_ref1 is where you measured 5V right?  In schematic this looks okay but that pad should never be 5V.  V_reg1 should be 5V as it is the supply for IC logic and VREF2.  Is there any other trace near the test point or capacitor that could be making contact?  I've never heard of this output being too high before, usually issues with VREF1 out of range are too low due to the pin being loaded.

    For the capacitors to GND on C pins I believe we recommend using 10nF, 100nF may place stress on the ESD structures between cells during cell connection.  But besides that this schematic looks good to me.

  • If I remember correctly, we watched VREF1 over time, and it would occasionally drop below 5V for a very short time. Every time it would dip, the ADCs would then read the cell voltages correctly for a couple cycles, then return to reading the scaled voltages upon VREF1 recovering to 5V. The chip also sometimes reports correct cell voltages for the first few cycles upon powering on before switching to the scaled ones. This behavior aligns with the voltages being 60% of expected, because the reference is 1/(60%) of what it should be.

    I should note that this issue only began to appear after the board was working perfectly for a few days. Some other copies of this board seemed to start off with this behavior. I wonder if there just isn't enough current for VREF1's zener diode to work? Are there other places you recommend probing?

  • I wonder if there just isn't enough current for VREF1's zener diode to work?

    If V+ were too low this could be a concern, but the direction of the failure doesn't make sense to me.  When VREF1 is off it should be 0V and when on ~3.15V.  With 5V I worry something may be damaged internally.

    Can you add a 10nF capacitor to the V+ pin to make sure it isn't related to V+ supply stability?

  • Added a 100 nF capacitor where you specified, and the issue persists. Measured VREF1 again and it's ~5.3V, while VREF2 is ~5.6V. This issue has been replicated on multiple boards. Is it possible the voltage reference fails high instead of low?

  • VREF2 is derived from VREG so it should not even be possible for it to exceed 5V.  Is VREG ~5V?

    Do you have the REFON bit of configuration register group A set throughout the test?  If not can you try setting it?

  • I repeatedly set REFON to 1 during the test. Later tonight I can verify using the RDCFGA command that it is actually being set. Assuming REFON is in fact 1, what do you think it could be? I'll also double check VREG with a multimeter but I believe it was similar to VREF1 and VREF2. Also, it's no problem if I send WRCFGA repeatedly as long as it's always REFON=1 right?

  • If it were to do with the reference turning off then REFON being set would prevent the reference from turning off.  If it remains set then the reference should stay on even if an ADC command is not actively running.  Repeating the WRCFGA will not create a problem.

    The easiest way to verify it is set is to send an RDCFGA afterward and check the REFON bit and PEC.

    Have you tested using an eval board?  From the schematic this looks okay but I'm worried some other net may be attached to VREF1 or VREF2.  Also please ensure the VREG is the expected 5V when the VREF1/VREF2 are high.

  • Sounds good. I have tested on an eval board and it worked fine. Our schematic only has the bypass caps on VREF1 and VREF2, though is it possible that too much load on VREG (say, from thermistors) could cause this issue? I tried disconnecting all the thermistors and still saw the same problem.