LTC6804-1: Internal Balancing Control Circuit

Hi Bryan,

What is the meaning of "where the balancing circuit may be stuck on without being commanded to", Does it mean that the chip automatically turns on the balance function when the chip does not receive the balance command, or that the FET cannot be effectively turned off after the balance command time is exhausted.

Figure 35 and the block diagram on page 18 were both right, It should be noted that the push-pull configuration was set between C(n) to C(n-1), rather than S(n) to C(n-1). 

The balancing pin is driven to a voltage level almost equal to the cell in the balancing-off state. I don't know how could you add a pull-up resistor between pins Cn and Sn. Can you sketch out the connection method you described and show it to me？

Thanks and Best Regards,

Frank

Hi Frank,

Thanks for the response!

I am still in process of isolating all the variables to determine the root cause, but we have seen that the balancing circuit is active (LED is lit in the diagram below) without being sent a message from the BMS Control MCU. We have also confirmed that the cell sense connections (in the connector) are unstable and we see floating voltages as well as abnormal activation of the balancing circuit. If either of the cell sense lines (positive or negative side of the cell) disconnect, is there a way for the balancing FET to enable due to floating voltage levels?

This is what I mean by pull-up resistor. Sorry I didn't mention that we are using external balancing.

What I am confused about is that Figure 35 shows a push-pull configuration, but the other diagram says there are only 12 FETs. A push-pull configuration should have 24 FETs for 12 balancing channels, so it leads me to think that there is only a pull down FET. In this case, when the FET is disabled, S(n) would be floating with respect to C(n), so a pull-up resistor would keep the FET off.

Thanks for the help,

Bryan Grant

Hi Analog,

Is there any update to this question?

Thanks,

Bryan Grant

Hi Bryan,

Sorry for the late response, I just happened to be on vacation recently.

First, you should check if the external MOSFET on your board is still working fine. In other words, it has to be good and undamaged.

If you can, please stabilize the cell sense connections. if you doubt either of the cell sense lines (positive or negative side of the cell) is disconnected. Sent Open-Wire Check (ADOW Command) to check directly.
The balancing function will not automatically open, its state depends on the DCC[x] bit setting even if floating voltages exist.

I don't recommend adding a pull-up resistor at the position you mentioned, because that configuration will make the impedance no longer larger enough when the MOSFET is off-state, but approximately equal to the pull-up resistor.

As mentioned above, 2 MOSFETs form the push-pull configuration, 1 MOSFET connected between Sn to Cn-1 for discharging cell. So the balancing function only needs 1 MOSFET but not 2, that is the point.

The push-pull structure is indeed made into the chip, Which is why both 24 MOSFETs and 12 MOSFETs statements will appear in the datasheet, but they were both correct statements, You need to understand the meaning it mentions according to the context

Thanks and Best Regards,

Frank

Hi Bryan,

To better understand the function of the push-pull structure in the chip I made the figure below, FYI.
by the way, the internal P-MOSFET was designed to allow the S pins to be used to drive the gates of external MOSFETs for higher discharge capability.

Thanks and Best Regards,

Frank

Hi Frank,

Thanks for the detailed answers. These responses answer my questions.

Bryan Grant

Hi Frank,

Sorry to respond again, but I'd like to clarify the recommendation for the pull-up resistor.

How high does the impedance need to be to be functional?

For context, we had determined on one board that the upper internal FET appears to have failed open, essentially floating the gate voltage and preventing the LTC6804 from opening the FET. On the same board, we added a 100kOhm pull-up resistor and were able to regain functionality of the balancing circuit when commanded.

Thanks,

Bryan

Hi Bryan,

In any case, from the perspective of theoretical circuit analysis, I think it is useless to add this pull-up resistor here. As for why it is useful in the actual circuit, I think it should be caused by other reasons, which may be related to your circuit board design and circuit connection method rather than the chip itself.

Thanks and Best Regards,

Frank

Hi Frank,

Ok, understood.

Thanks,

Bryan

Hi Frank,

Ok, understood.

Thanks,

Bryan