We have experienced some issues where the balancing circuit may be stuck on without being commanded to, so I'm interested in understanding what the internal FET configuration of the balancing control pin is. Can you clarify this?
In the datasheet, figure 35 indicates that there is a push-pull configuration while the block diagram on page 18 seems to indicate that there is only one balancing FET per channel.
Ultimately, is the balancing pin being driven to a the upper cell voltage in the balancing off state or is it floating? Would you recommend adding a pull-up resistor between pins Cn and Sn to ensure the FET is off in an off state?