Question about how to make Vreg output voltage of LTC6811-2

1. No, you must toggle CS to wake the part and generate VREG.  Alternatively 5V can be provided externally, in which case it may always be kept on.
2. Correct.  CS must be pulled low or a differential signal placed across the isoSPI
3. Initial power on state will be standby, the IC enters sleep with DRIVE turned off only after the watchdog timeout, typically 2s
4. What is TR?  There is no way to use DRIVE to generate VREG without sending CS pulse.  Using external regulator for always on 5V VREG is the only way to have a constant 5V VREG.
5. Upon initially receiving power the board is in standby with VREG active for 2s before the watchdog timeout, at which point it enters the sleep state.
6. Yes, any CS low pulse or wakeup command will reset the 2 second watchdog timeout.

Dear mvrablic !

In my first design I powered VREG from a buck controller (always on). Waking up the chip from my MCU was no problem and I have been using 5/3.3V level shifters as suggested.

With my new design I want to shut down the buck controller (this is unfortunately not shown on your "typical application" notes in the docs and your "reference design kits" use the NPN method which is not very sophisticated imo).

Now my question: When the device sleeps VREG will be 0V and driving the 4 wire SPI will exceed the absolut maximum ratings even when driven by 3.3V pull-ups only. All the other modules in the stack will be using IsoSPI so the problem only exists for the lowest module. Is it even possible to wake the device up from a 4 wire SPI if VREG is not supplied externally ?

Input Voltage (Relative to V–)
C0 –0.3 V to +6 V
C18 –0.3 V to MIN ( V+ + 5.5 V, 112.5 V)
C(n), S(n) –0.3 V to MIN (8 × n, 112.5 V)
IPA, IMA, IPB, and IMB –0.3 V to VREG + 0.3 V, ≤ 6 V
DRIVE –0.3 V to +7 V
All Other Pins –0.3 V to +6 V

I am designing a PCB and this should work from the beginning .....

Thx, Tom

CSB or SCK activity will wake up the part when it is sleeping, even when the IC is sleeping and VREG 0V.  I agree that this is confusing from the absolute maximum table though.  Per figure 37 these pins have a 12V ESD structure referenced to GND, not an ESD structure referenced to VREG.  

ViennaTom said:

With my new design I want to shut down the buck controller (this is unfortunately not shown on your "typical application" notes in the docs and your "reference design kits" use the NPN method which is not very sophisticated imo).

The reasons NPN is recommended over buck converter are cost related and safety related.  If the extra cost and more failure modes with a separate buck converter IC are acceptable for your application then it works too.  Also note that when DRIVE is off and the part is sleeping no power is dissipated in the NPN at all, so the power consumption wasted is only applicable during active operation of the IC, not when the system it is in is idle.

mvrablic Thank you so much for your quick reply !!!! So it seems to be safe to pullup the CK and CS while the controller is asleep. I chose a buck controller with minimum sleep current and will control it with DRIVE. The reason is, that I have to power additional circuitry (current sensors, I2C ADC) and the NPN solution would burn too much power. I am not sure if it is enough to power the level shifters with 3.3V through a Schottky and 5V from VREG through another Schottky once this is available. According to the SPI levels this should work.

Yes, this should work.  Make sure to leave enough time for the buck converter startup between sending the wakeup and attempting communication.