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Question about how to make Vreg output voltage of LTC6811-2

Category: Hardware
Product Number: LTC6811-2


My customer is developing BMS system with  LTC6811-2.

And they  ask some questions about booting procedure in LTC6811-2.

LTC6811 LSI is in the initial state (POWER-ON), 

Q1) Is there an external setting method that can wake-up without processing CS PORT command?

Q2) Is there no external H/W Setting that can output the voltage of the DRIVE terminal?

Q3) In the initial power-on state(sleep mode),  .. (same as  LTC6803 in the initial state)

Q4) Is there any way to use Vreg power using TR without processing s/w cs command ?

Just after powerring on the board (supplying power to LTC6811-1), they think that LTC6911-2 is a sleep mode.

So for getting a voltage at Drive terminal,they think that they should do a wake-up signal thru CS pin from Micom.

Q5) Is above description right?

Q6) Can they make a 5.7V output voltage at DRIVE terminal without a ake-up signal (CS is low) from Micom (additional command) or other additional procedure?

They want to use Vreg output  voltage initial state (jusrt after power- on.).

So they need your advices.



  • Dear !

    In my first design I powered VREG from a buck controller (always on). Waking up the chip from my MCU was no problem and I have been using 5/3.3V level shifters as suggested.

    With my new design I want to shut down the buck controller (this is unfortunately not shown on your "typical application" notes in the docs and your "reference design kits" use the NPN method which is not very sophisticated imo).

    Now my question: When the device sleeps VREG will be 0V and driving the 4 wire SPI will exceed the absolut maximum ratings even when driven by 3.3V pull-ups only. All the other modules in the stack will be using IsoSPI so the problem only exists for the lowest module. Is it even possible to wake the device up from a 4 wire SPI if VREG is not supplied externally ?

    Input Voltage (Relative to V–)
    C0 –0.3 V to +6 V
    C18 –0.3 V to MIN ( V+ + 5.5 V, 112.5 V)
    C(n), S(n) –0.3 V to MIN (8 × n, 112.5 V)
    IPA, IMA, IPB, and IMB –0.3 V to VREG + 0.3 V, ≤ 6 V
    DRIVE –0.3 V to +7 V
    All Other Pins –0.3 V to +6 V

    I am designing a PCB and this should work from the beginning .....

    Thx, Tom

  • Thank you so much for your quick reply !!!! So it seems to be safe to pullup the CK and CS while the controller is asleep. I chose a buck controller with minimum sleep current and will control it with DRIVE. The reason is, that I have to power additional circuitry (current sensors, I2C ADC) and the NPN solution would burn too much power. I am not sure if it is enough to power the level shifters with 3.3V through a Schottky and 5V from VREG through another Schottky once this is available. According to the SPI levels this should work.