Post Go back to editing

LTC6811 Jitter / Sample&Hold

Category: Hardware
Product Number: LTC681x

I am using and a LTC6811 in my master thesis and i want to precisely time the Sampling. There is a expected time after sending the LTC6811_adcvax command, but i can't find any hint in the Datasheet regarding the Jitter.
Are there some additional information existing regarding the Sampling jitter? 
Based on my expectation of the Noise at the input (C1) caused by a Sample & Hold stage. So roughly estimated there is a ~34µs jitter.
Can an analog engineer provide some information about the Sample &Hold stage and/or about internal clock structures?

Any suggestions to further reduce the Sampling jitter are welcome Slight smile
kind regards,

  • Thank you for your inquiry. I am looking into this and will get back to you as soon as possible.

  • You can expect a maximum 10% error in the ADC Clock frequency.
    As the ADC Sampling frequency of LTC6811 is 3.3MHz, the clock's frequency can vary anywhere between 2.97MHz to 3.63MHz. 
    Can you explain more about how you are estimating the above-mentioned sampling jitter? And when you were measuring, did you have an anti-aliasing filter in between your source and the Cell Input pins of LTC6811 as described in the applications information of the datasheet?

  • Thx   for your reply,
    Good to know about this ADC Sampling frequency.
    In my application there is an anti-aliasing filter in between the battery cells and the Cell Input pins.
    For this test measurement no anti-aliasing filter was in place, to get some insights about the ADC timings. 
    I am using the Devkit DC2259A and remove the capacitor on purpose to see some sample&hold action.
    This 10% clock is more or less normal variation or +-10% variation over the whole temperature range?
    So i have to assume the conversion time also varies by 10%?
    I would be happy if you can also give some insights about the internal sampling stage of the LTC6811.
    Kind regards,