Question about Daisy chain configuration of LTC6812-1

If you are planning on using LTC6812 then we recommend you to use the transformer coupling only. Capacitive coupling is for next generation parts.

Let me give you more details on the transformer coupling - 

The transformer which is selected for the design must have a continuous isolation rating that exceeds the full pack potential (e.g. 400V), thus a HiPot test rating of >3kV is generally required, such as with an ESMIT-4180 part. Transformers with HiPot of 1.5kV or lower are actually only rated for about 80V of continuous bias since the wire varnish will have pores that can allow corrosion & electro-migration. Transformer layout practices should include circuit-board slotting to maintain the best HV creepage spacing across the dielectric barrier. For IC’s with isoSPI biasing control resistors, the receiver slicing should generally be set to ±500mV accordingly (not shown: RB1 = 1kΩ and RB2 = 1kΩ). You can refer to this link for for the reference design with transformer. https://www.analog.com/media/en/technical-documentation/eval-board-schematic/dc3036a-schematic.pdf  

If you want to design with newer parts (for which capacitive coupling is recommended) and have queries related to it you will have to ask your question on bms.support@analog.com . 

If you are planning on using LTC6812 then we recommend you to use the transformer coupling only. Capacitive coupling is for next generation parts.

Let me give you more details on the transformer coupling - 

The transformer which is selected for the design must have a continuous isolation rating that exceeds the full pack potential (e.g. 400V), thus a HiPot test rating of >3kV is generally required, such as with an ESMIT-4180 part. Transformers with HiPot of 1.5kV or lower are actually only rated for about 80V of continuous bias since the wire varnish will have pores that can allow corrosion & electro-migration. Transformer layout practices should include circuit-board slotting to maintain the best HV creepage spacing across the dielectric barrier. For IC’s with isoSPI biasing control resistors, the receiver slicing should generally be set to ±500mV accordingly (not shown: RB1 = 1kΩ and RB2 = 1kΩ). You can refer to this link for for the reference design with transformer. https://www.analog.com/media/en/technical-documentation/eval-board-schematic/dc3036a-schematic.pdf  

If you want to design with newer parts (for which capacitive coupling is recommended) and have queries related to it you will have to ask your question on bms.support@analog.com .