1. Duration of delay after changing CSB
We soon will have a STM32L431 connected to a single ADBMS1818 on the same board with 4 wire SPI. The delays required following the setting of CSB low and high are not clear. Does the datasheet Rev A, Table 41, SPI Master Timing delays apply in our direct SPI connection case (but might only apply to the isoSPI daisy-chain situation)? Studying some Linduino code on github for the LTC681x I did not find anything indicating that delays were added, e.g. the CSB was set low and the SPI routine called in the next instruction. This suggests that setting the CSB low before starting the SPI, which could be a fraction of a usec, is sufficient.
2. Datasheet Rev A, Table 46. Write/Read PEC Format: I assume this is a minor typo--
Row PEC0, Column Bit 0, should be PEC, bit 7, not bit 17.