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ADBMS1818 CSB delay

Category: Software
Product Number: ADBMS1818

1. Duration of delay after changing CSB

We soon will have a STM32L431 connected to a single ADBMS1818 on the same board with 4 wire SPI. The delays required following the setting of CSB low and high are not clear. Does the datasheet Rev A, Table 41, SPI Master Timing delays apply in our direct SPI connection case (but might only apply to the isoSPI daisy-chain situation)? Studying some Linduino code on github for the LTC681x I did not find anything indicating that delays were added, e.g. the CSB was set low and the SPI routine called in the next instruction. This suggests that setting the CSB low before starting the SPI, which could be a fraction of a usec, is sufficient.

2. Datasheet Rev A, Table 46. Write/Read PEC Format: I assume this is a minor typo--

Row PEC0, Column Bit 0, should be PEC, bit 7, not bit 17.

Top Replies

  • Does the datasheet Rev A, Table 41, SPI Master Timing delays apply in our direct SPI connection case


    No, that corresponds to the timing specifications of the 3-wire SPI Initiator that…

  • Does the datasheet Rev A, Table 41, SPI Master Timing delays apply in our direct SPI connection case


    No, that corresponds to the timing specifications of the 3-wire SPI Initiator that can be configured on the GPIOs in ADBMS1818. 

    The time between the CSB falling edge to SCK rising edge should be minimum 1us. You can find more about all the SPI timing requirements in SPI Timing Specifications subsection(Page no.9) under Specifications section in ADBMS1818 Datasheet Rev.A.  You can also find example timing diagram in Figure 77(Page no.45). 

    Row PEC0, Column Bit 0, should be PEC, bit 7, not bit 17.

    Yes its a typographical error. It is PEC bit 7 and not PEC bit 17. Thanks for pointing out. It will be updated in next datasheet revision.