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Battery management System

Category: Datasheet/Specs
Product Number: LTC6804-2
Software Version: I don't know

Hello,we have a question about your product,we read both LTC6802-2 datasheet and LTC6804-2 datasheet.İn the LTC6802-2 datasheet while making a daisy chain we saw that highest cell of the lowest IC is connected to lowest cell of the next higher IC(page 11).However we never came across the same usage in the LTC6804-2.İs there a difference in this connections because of isoSPI? And we cannot have 5v output from the Vreg pin, we couldn't understand whether it was a input or output can you help us?

  • VREG is a 5V input, but it is generated from the cells attached to the IC by using an NPN transistor such as NSV1C201MZ4 attached to the DRIVE pin.  See the typical application circuit from the LTC6804-2 datasheet below for how this is implemented: 

    The LTC6802 as it's quite an old part and not recommended for new designs.  But for any BMS, the batteries and cell monitors are stacked in series.  You can think of each LTC6804 as if it were a single, independent, 12s module.  Multiple modules can be stacked in series or parallel to generate the desired pack voltage and capacity.  So this means that the positive side of one 12s module is electrically the same node as the negative side of the next module.  isoSPI allows communication between the multiple ICs without needing to worry about level shifting the SPI between every IC throughout the pack.  It does not impact the arrangement of the monitors themselves in the pack.