Hello all,
I am a student who is having an issue with their PCB design. I am attempting to use a 6813-1 to passively discharge 18 cells. I have a PCB that when cells are attached has voltages appear all over the board in ways I cannot explain, that and the chip begins to overheat and burn out. I am stumped as to why this is occurring. I assume I am either missing something with my schematic or the board layout is faulty.
As for how I am attaching the cells, I start from the lowest potential position attaching a cell between C0 and C1, then in between C1 and C2 and so on until I have 5 cells on the board. Around the fourth cell is when the chip starts heating up, however discharge paths will begin to open on their own as soon as the second cell is placed. I have tried removing the chip and found that the voltage stops appearing on the gates of the P-Channel FETs that open/close the discharge path.
To clarify and restate, when I attach cells to the board, the chip seems to allow voltage on the S pins, even before the chip turns on.
As for powering the chip, I short the highest potential cell's anode to the V+ pin and I expect the simple linear regulator specified in the data sheet would regulate Vreg to 5V. That being said, Vreg was never generated, for the LED attached to its location never lit.
Figure 1. LTC6813 and peripherals, the four wires going off the the top of the page are Iso-SPI lines.
Figure 2. 3 highest potential discharge traces, there are 18 identical discharge paths total.
Figure 3. PCB, where each cell is attached in between the Bx square pads. There are also internal discharge traces and a ground plane that are not shown.
I am really looking for any explanations as to why these voltages are moving through the chip into the s-pins.
I would appreciate any advice, or any obvious remarks about things my design is missing. Thanks,
