Hello,
I am new to the forum so thanks for indulging me and sorry for any inconsistencies from other posts.
I have used a LTC6804 before and am working on a new project using LTC6810. We are at the start of the project and have started on schematics and software documentation. This is a large system with many of these chips involved in a complex series parallel series parallel arrangement of cells.
My question 1 is, will the LTC6810 not allow me to turn on adjacent S pins, in the external discharge circuit application?
For example, if I want to turn them all on would it simply ignore my command?
I noticed that the LTC6810 arranges its internal discharge FETs different from other chips like the 6804 in that it connects the S pin to another S pin directly with no C pin connection. I also noticed that the datasheet says, because of this you cannot have adjacent discharge pins activated or it will effectively ignore the command to do so, in my interpretation. This is different than any of the other LTC68xx chip datasheets I have looked at so far.
"The LTC6810 does not allow adjacent discharge switches to be asserted, so the WRFG command will not be executed if adjacent DCC bits in the CONFIG register are asserted. The current path shown at the right of Figure 40b shows that if adjacent discharges switches were permitted to be on, discharge current would flow through the series combination of cells instead of the individual cells."
In our implementation we will use external FETs connecting the S lines to the gate externally. So, if I want to turn them all on, will it ignore my command? It says, " The S pins can act as digital outputs suitable for driving the gate of an external MOSFET or the base of an external NPN as illustrated in Figure 41. "
Question 2: Does this mean there is a configuration to switch it to external which may allow me to turn on adjacent/all S pins and/or use the S pins as digital outputs to drive the External Discharge Circuit configuration. Because I cannot find it, so my assumption is that the datasheet is just pointing out that you could use it this way and it would inherently work.
To dig further into this, this chip has the workaround ability to read and balance a 7th cell which I think has confused the issue on how the S pins are to be used for balancing. In the 6-cell scenario, judging by what I see in the datasheet, I think pins S1 though S6 are intended for the normal 6 cells, and S0 is intended for the extra 7th. The difference being that for a 6-cell arrangement, one of the S pins is not clearly defined on what should be done with it.
Question 3: Should the unused S pin, which I will say is S0, be left floating or tied to anything specific in the 6-cell use?
If so, I think Figure 41 should actually start at S1 in the datasheet, but either way it would be more clear to do a diagram similar to that at the end of the datasheet showing the bottom and top connections and abstracting away the repeating middle to show what to do with the top and bottom connections.
Side note, I think WRFG quoted above is a typo in the datasheet as I cannot find a reference, should it be WRCFG? Is this the right forum to suggest datasheet updates?
Reference: https://www.analog.com/media/en/technical-documentation/data-sheets/LTC6810-1-6810-2.pdf
looking at Rev A of that document.
