Hello,
I am looking forward to using the AD8450 with batteries up to 42V. The Bus voltage would be 48V. Within specs from what I understand.
The 42V with the lowest PGDA gain (0.2) will lead to a worst case loop error of 8.4V, which is over the control voltage range for the ADP1974 I intend to connect to the VCTRL pin as in the application note/reference design.
I see two ways to deal with the problem:
1 - add 400k worth of resistor in the PGDA input ladder in order to get a gain of 0.1 V/V. Would use 0.1%, 10ppm to 25ppm resistors.
2 - scale the output of the PGDA (BVMEA) by factor of 0.5 with divider opamp, set PGDA gain to 0.2 V/V.
Any of these lead to less bandwidth, more noise and possible loop stability issues...
I would appreciate feedback on these or other recommended solutions.
Kind regards,
Ricardo