I have ran the Design Tool and exported the Bode+LoadTransient+Ripple file for simulation in ADISimPE. I started with the configuration of the first figure below for sanity check (I ultimately want to simulate the circuit with a LC filter for minimum ripple). I am getting some funny results with the bode simulation.
Bode plot in the Design Tool:
ADISimPE bode plot:
It reports a nearly 0 gain margin and -158° phase margin and that may explain the oscillation in the transient simulation graph:
I am attaching the ADISimPE file created by DT that generated the two graphs above. What am I missing?
Thank you in advance for the support.
PS: I am hope I am posting in the right place, ADIsimPE appears with a "Power By Linear" that implies Linear Technology solutions though the particular IC I am using is AD.
Verified Answer: RE: ADP2384 Design Tool vs ADISimPE results by ezadminThis question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.
Question: RE: ADP2384 Design Tool vs ADISimPE results by EVC
Hello, no clue about this issue? I would love to design with this IC but I would feel more comfortable having some trustworthy simulation results to back it up.
According to your design spec of output ripple, it is required that the ripple value is smaller than 5mV. So a second LC filter is needed to suppress the ripple.
If a second LC is used and the feedback point is directly from Vout only using a resistor divider, then the loop may have stability issue. we recommend to add another cap (~10nF) between the first LC output point and FB pin. That will help to stable the loop.
Thank you for your response.
It does not address my concerns though. The SIMPLIS file was exported by the excel spreadsheet. I tried a more conservative design, with 2% ripple but the circuit exported to SIMPLIS is still unstable.
So the question is still which result should I rely on, the spreadsheet's or SIMPLIS's?
I noticed that the Simplis schematic file exported from the excel tool has an extra Cff (1nF) which is not needed in the design.
When removing the Cff and run the simulation file again, you will get the result as below:
The regulator is stable. Basically, you can trust both excel and simplis simulation result. Just make sure the simplis schematic matches with the excel settings.
Here is the picture files, not sure why they are not shown on the previous reply.
Thanks for the heads up.
I noticed the capacitor but forgot to eliminate it from the schematics. It is stable but results do not match: compare crossover frequency, gain and phase margins and the graphs themselves. I suppose SIMPLIS's results are more trustworthy.
I suggest the tools undergo a review. The IC looks to be very good but the tool needs improvement. I wonder if one can trust the thermal performance data.