Original Question: Is there any way to fully simulate the ADP5054 with Buck 1 and Buck 2 in parallel? by snewberry
I'm designing a multi-rail power supply with the ultimate goal of minimizing board area. Our current design uses LT uModules but I really like the features in the ADP505x series. I'll be doing a design which is very similar to the Kintex UltraScale refrence design in the first few pages of this (PDF) document.
I want to validate the design with full simulation. I've been using the ADP505x Buck Designer Excel spreadsheet, and I've exported models of single buck converters out to ADIsimPE. I see that those models note that parallel operation is not included. Is there some beta version of the model that includes the parallel operation? I'd really like to see the output of a full, dual IC power supply.
Thank you for your help.
We do not have plans for a parallel model. However, there is a way to simulate the situation reasonably well, though it will not exactly follow the actual schematic since we have not given the user a way to turn off the error amplifier of the second channel. I have attached a reference design as an example which was made in this exact same way.
1. Use ADIsimPower to create a design that meets your design requirement.
2.Output channel 1 or channel 3 depending on if you have channels 1+2 in parallel or 3+4.
3.Ignore the red error warning telling you we do not have a parallel mode model.
4. Cut and paste the entire circuit so there are now 2 complete ADP505x circuits.
5. Connect Vouts and Vins together and delete the extra SW net label, Vout net label, vout probe, bode plot probe, EXT_CLK component, and vin supply (now labeled vin1).
6. Delete the second channel's feedback components and short the feedback nodes together.
7. Short together the COMP voltages LEAVING the components. These compensation components will have to stay the same, otherwise the simulation will be invalid.
8. Set the jumpers correctly so you are using the external clock for each channel.
9. Add a ground referenced inverter from the advanced digital components library found in the "Place" pull down.
10. Connect the EXT_CLK output to the input of the inverter and the outputs to the two ICs SYNC pins, and a GND symbol to the ground pin.
11. Move the SW pin label from the switch node to the output of the EXT_CLK component. (remember we deleted the SW label from the switch node of channel 2). You will see that the POP probe located in the far upper right corner is connected to the SW net, which we have now connected to the EXT_CLK which we are using to clock the system.
12. Run simulation.
13. If you run out of topologies, double check that you followed everything above correctly. Then back annotate the initial conditions and run again.This will allow the simulation to begin closer to steady state.
Awesome, thank you very much for your help.