What are some important considerations when selecting a DAC or ADC for a specific application?
Prior to deciding upon either a DAC or an ADC, you’ll want to consider all requirements for the design. Pricing can vary significantly, and you’ll also want to consider the full system cost. A lower cost DAC or ADC may not provide the most economical system overall. With the DAC output frequency, it’s worth considering Direct-RF techniques. Direct-RF techniques can help improve phase noise, reduce component counts, and provide a simplified RF cascade that results in better overall performance.
If the desired frequency can’t be met with the Direct-RF DAC, it may be possible to use an alternate Nyquist zone of that DAC, but be aware of challenges with impairments like sinx/x or reduced signal power from the DAC. The design and placement of anti-alias filters in the RF chain are critical to avoid the generation of in-band intermodulation products. Alternatively, many DACs are available with integrated upsampling or baseband processing which can simplify the design, save power, and reduce cost when using an FPGA. The alternative to a Direct-RF DAC is the traditional DAC and IQ modulator approach that can be the more cost-effective and a preferred solution in many designs.
If the bandwidth of the signal is narrowband, the IQ modulation techniques become a better solution. Be aware that I/Q modulation can have carrier feed through and I/Q imbalance, although parts are getting better at addressing this. If I/Q modulation performance isn't good enough and Direct-RF is not an option, consider mixing up to low IF and then use IQ modulation to get to RF. IQ modulation will require appropriate RF design to filter out carrier bleed through and undesired sideband.
A leading factor in the DAC selection should include signal fidelity. System performance: SNR, EVM, MER, group delay, and amplitude ripple all can drive the decision criteria and all other decisions that impact this performance. Typically the faster a DAC and the more bits resolution, the higher performing DAC is. An example of this trade-off is group delay and amplitude ripple, these may become a problem if sharp filter edges are required to meet out-of-band requirements, and that will ultimately affect EVM / MER. The clock circuit that drives the sampling clock of the DAC also affects performance. Integrated PLL/VCO IC's are cost effective and provide adequate phase noise for many applications, but for lowest phase noise a discrete single frequency VCO and PLL IC is required.
The RF circuit must provide the required output power. The signal level from the DAC defines a part of that RF circuit. Optimizing the DAC dynamic range can simplify the design by reducing an extra power amplifier stage. When selecting an ADC, the input frequency range and bandwidth are important as well. With high-speed ADC's, they’re generally more expensive than lower speed ADC's, so it’s typically desirable to use the lowest speed ADC that meets the requirements. To achieve higher levels of performance it’s often required to go with the higher speed ADC, although that’s not the only factor that defines ADC performance. There may also be built-in ADC functionality available with built-in tuners, this can save money at the system level by reducing resources required in an associated FPGA.
The required bandwidth can also drive the speed of the ADC required. A low-bandwidth signal can be digitized with a high-speed ADC or a lower speed ADC with the RF circuits supplying bandwidth restricting filters and tuners is another consideration. The SNR, EVM, MER, group delay, and amplitude ripple requirements can drive much of the ADC decision. Different fidelity requirements will have an impact on the ADC selection. The number of bits in the ADC will have a significant effect on the EVM / MER performance. The group delay and amplitude ripple will have an effect on the overall EVM / MER capability in the design.
Out-of-band signals should be considered, as they can interfere with your signal of interest. Be aware of how far in frequency these out-of-band signals are from the signal of interest, and also what their relative amplitudes are. High amplitude out-of-band signals can cause problems with intermodulation products, desense the receiver and impact gain control functions.
A variety of factors including the lowest receive signal level, the input range, and ADC full-scale voltage determine how much analog / RF gain is required. Consider the power in out-of-band signals when designing the circuit topology, it may affect the placement of filtering and the amount of gain control needed and impact the number of bits needed in the ADC. The selected ADC can make the RF circuit design less challenging, but also consider that the ADC must be able to support the instantaneous dynamic range of the intended application.
Finally, phase noise on an ADC is an important factor to consider. With mixing stages placed in front of the ADC, the phase noise of those stages must be sufficiently effective when combined with the ADC to meet the system requirements. Phase noise from successive mixer stages will cascade. The phase noise from the sampling clock to the ADC is critical to the successful implementation of a receiver. Excessive jitter on the ADC clock degrades the performance of the ADC, as it essentially reduces the number of effective bits in the ADC. Integrated PLL/VCO IC's are cost effective and provide adequate phase noise for many applications. Note the lowest phase noise of a discrete single frequency VCO and PLL IC is required.
This is not a complete list of all design considerations, however, it does indicate the complexity and importance of selecting the appropriate DAC and ADC for a design. SED offers a variety of design services ranging from turn-key manufactured circuit cards built-to-spec, hardware schematic designs, and design reviews.
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