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Issue in implementation of HDL verilog codes after run in VIVADO 2021.1

Category: Software
Product Number: RADIOCARBON-13
Software Version: VIVADO 2021.1

Issue details are

Tool used: Vivado 2021.1

MPSoC Device Used: Xczu3cg-sbva484-1-e

Files used in the project: radiocarbon-13_Testing/bytepipe_sdk-main/src/adrv9001/hdl

High level Issue: Implementation Failed.

Error wind message in VIVADO Tool:

Implementation

Design Initialization

[Designutils 20-1280] Could not find module 'ila_axis'. The XDC file g:/PULLARAO/TECH/PROJECTS/RADIOCARBON-13/RADIOCARBON-13/PULLARAO/CODES_TESTING/FPGA/project_2.srcs/sources_1/ip/ila_axis/ila_v6_2/constraints/ila_impl.xdc will not be read for any cell of this module.



Place Design

[Place 30-415] IO Placement failed due to overutilization. This design contains 326 I/O ports

while the target device: xczu3cg package: sbva484, contains only 297 available user I/O. The target device has 297 usable I/O pins of which 0 are already occupied by user-locked I/Os.

To rectify this issue:

1. Ensure you are targeting the correct device and package. Select a larger device or different package if necessary.

2. Check the top-level ports of the design to ensure the correct number of ports are specified.

3. Consider design changes to reduce the number of I/Os necessary.


[Place 30-68] Instance adrv9001_rx1_inst/i_serdes/IBUFDS_inst/DIFFINBUF_INST (DIFFINBUF) is not placed


[Place 30-99] Placer failed with error: 'IO Clock Placer failed'

Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.


[Common 17-69] Command failed: Placer could not place all instances

Below is the issue screen shot


  • I can't seem to replicate your issue.

    Try using bytepipe_sdk  .zip folder from git again

    • download
    • unblock zip folder commends like mentioned in my september 25th reply
    • unzip to the C: drive so that the src folder is two folders down from the C: Drive (C:/bytepipe_sdk/src/...)
    • source vivado tools
    • make hdl

    If that doesn't work, then the axi_dma cloning process is probably still breaking your build. Perhaps you're having permissions issues when cloning content from a network location

  • Sir we tried what you told in above reply but getting stuck at same place i.e when we building axi_dma.

    This sh file was provided in bytepipe_sdk in axi_dma folder which i opened through notepad. In this  middle two commands for upack2 and cpack2 we are getting OK conditions as you can see in above screenshot but adi_ip_xilinx.tcl and axi_dmac xilinx are not getting build properly and some error are coming which you can see in above screenshot.

    But these all files are getting cloned from the same path github repo only hdl_2021_r1 is used instead of what is highlighted in this notepad screenshot.

    Please do the needful.

  • I looped in some other team members to look at this issue. They are going to set up a clean build environment with freshly downloaded tools. Hopefully, this will get closer to replicating your environment and reveal similar problems.

    I'll let you know their results.

  • Ok Thankyou Sir.

    But today morning we came and tried again by doing some changes as u mentioned above and some modification from our side by setting those paths and environment variables we successfully able to build all the files and at last able to get .xsa file 

    Screenshots are attached 

    Further in future if your support and guidance is required will come to you sir.

  • Sir we started building the rflan sw after successfully building hdl  but we got the following errors:

    cp: cannot stat '/cygdrive/c/bytepipe_sdk/workspace/rflan/rpu_system/Debug/sd_card': No such file or directory
    cp: target '/cygdrive/c/bytepipe_sdk/workspace/rflan/sd_card' is not a directory
    cp: cannot stat '/cygdrive/c/bytepipe_sdk/workspace/rflan/rpu/Debug/rpu.elf': No such file or directory
    cp: cannot stat '/cygdrive/c/bytepipe_sdk/workspace/rflan/rpu/Debug/rpu.elf.size': No such file or directory
    cp: cannot stat '/cygdrive/c/bytepipe_sdk/workspace/rflan/rpu_system/Debug/sd_card/BOOT.BIN': No such file or directory
    zip warning: name not matched: rflan/sd_card/

    zip error: Nothing to do! (try: zip -rj /cygdrive/c/bytepipe_sdk/workspace/rflan/rflan_xczu3cg-sbva484-1-e_sdcard.zip . -i rflan/sd_card/)
    adding: fsbl_a53.elf (deflated 68%)
    adding: pmufw.elf (deflated 61%)
    adding: rflan_xczu3cg-sbva484-1-e.xsa (deflated 6%)

    we followed this video also, but in the place of last two commands shown in video screenshot we are getting above errors and not getting rflan/sd_card folder.

    Please do the needful.

  • Sorry for the delay. I was on vacation Monday and Tuesday of this week.

    Could you check C:/bytepipe_sdk/workspace/rflan to see if you have a file named "rflan_xczu3cg-sbva484-1-e.xsa"?

    Attempting to build "sw" with rflan_xczu3cg-sbva484-1-e.xsa missing from C:/bytepipe_sdk/workspace/rflan produced similar errors for me.

  • Ok no problem sir .

    This is my another account login. 

    "rflan_xczu3cg-sbva484-1-e.xsa" this file is already present in the same path or directory as you mentioned above.

    we executed building rflan sw but got some error regarding sdcard related.

    screenshots are attached for your reference.

    Please do the needful.