Post Go back to editing

Issue in implementation of HDL verilog codes after run in VIVADO 2021.1

Category: Software
Product Number: RADIOCARBON-13
Software Version: VIVADO 2021.1

Issue details are

Tool used: Vivado 2021.1

MPSoC Device Used: Xczu3cg-sbva484-1-e

Files used in the project: radiocarbon-13_Testing/bytepipe_sdk-main/src/adrv9001/hdl

High level Issue: Implementation Failed.

Error wind message in VIVADO Tool:


Design Initialization

[Designutils 20-1280] Could not find module 'ila_axis'. The XDC file g:/PULLARAO/TECH/PROJECTS/RADIOCARBON-13/RADIOCARBON-13/PULLARAO/CODES_TESTING/FPGA/project_2.srcs/sources_1/ip/ila_axis/ila_v6_2/constraints/ila_impl.xdc will not be read for any cell of this module.

Place Design

[Place 30-415] IO Placement failed due to overutilization. This design contains 326 I/O ports

while the target device: xczu3cg package: sbva484, contains only 297 available user I/O. The target device has 297 usable I/O pins of which 0 are already occupied by user-locked I/Os.

To rectify this issue:

1. Ensure you are targeting the correct device and package. Select a larger device or different package if necessary.

2. Check the top-level ports of the design to ensure the correct number of ports are specified.

3. Consider design changes to reduce the number of I/Os necessary.

[Place 30-68] Instance adrv9001_rx1_inst/i_serdes/IBUFDS_inst/DIFFINBUF_INST (DIFFINBUF) is not placed

[Place 30-99] Placer failed with error: 'IO Clock Placer failed'

Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.

[Common 17-69] Command failed: Placer could not place all instances

Below is the issue screen shot