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AD9364 CMOS line length matching requirement

We are making a new board with AD9364. We are following the ADALM pluto reference design. We have seen special patterns on the CMOS data lines. Is it for length matching? What is the criteria for it? What is the maximum length permitted in CMOS mode? What should be the limit for the skew between the data and clock lines? How these patterns are made-just to adjust the length? Is it a manual routing or any tool to compute these pattern?

We have seen that the length of Rx data clock and frame clocks are having twice the length of data lines whereas the tx clock and frame signals are having same length as those of data lines. What is the criteria for these lengths? Why FB Clock doesn't have serpentaine routing? 

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[edited by: Jobin at 2:12 AM (GMT -4) on 30 Mar 2021]
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