9009+706 petalinux

hello,I export hdf file from vivado2018.3 which provided by ADI github 2019_r1 HDL project.And then use this hdf to build image in petalinux2018.3, it can config normally but when do petalinux-build it get error.as following

petalinux-build

[INFO] building project
[INFO] sourcing bitbake
INFO: bitbake petalinux-user-image
Loading cache: 100% |############################################| Time: 0:00:01
Loaded 3444 entries from dependency cache.
Parsing recipes: 100% |##########################################| Time: 0:00:03
Parsing of 2569 .bb files complete (2536 cached, 33 parsed). 3445 targets, 149 skipped, 0 masked, 0 errors.
NOTE: Resolving any missing task queue dependencies
Initialising tasks: 100% |#######################################| Time: 0:00:07
Checking sstate mirror object availability: 100% |###############| Time: 0:00:17
NOTE: Executing SetScene Tasks
NOTE: Executing RunQueue Tasks
ERROR: device-tree-xilinx+gitAUTOINC+b7466bbeee-r0 do_compile: Function failed: do_compile (log file is located at /home/zlh/Desktop/petalinux_706/build/tmp/work/plnx_zynq7-xilinx-linux-gnueabi/device-tree/xilinx+gitAUTOINC+b7466bbeee-r0/temp/log.do_compile.33532)
ERROR: Logfile of failure stored in: /home/zlh/Desktop/petalinux_706/build/tmp/work/plnx_zynq7-xilinx-linux-gnueabi/device-tree/xilinx+gitAUTOINC+b7466bbeee-r0/temp/log.do_compile.33532
Log data follows:
| DEBUG: Executing shell function do_compile
| Error: /home/zlh/Desktop/petalinux_706/build/../components/plnx_workspace/device-tree/device-tree/pl.dtsi:36.32-33 syntax error
| FATAL ERROR: Unable to parse input tree
| WARNING: /home/zlh/Desktop/petalinux_706/build/tmp/work/plnx_zynq7-xilinx-linux-gnueabi/device-tree/xilinx+gitAUTOINC+b7466bbeee-r0/temp/run.do_compile.33532:1 exit 1 from 'dtc -I dts -O dtb -R 8 -p 0x1000 -b 0 -i /home/zlh/Desktop/petalinux_706/build/../components/plnx_workspace/device-tree/device-tree -i /home/zlh/Desktop/petalinux_706/build/tmp/work-shared/plnx-zynq7/kernel-source/include -i /home/zlh/Desktop/petalinux_706/build/tmp/work-shared/plnx-zynq7/kernel-source/include -i /home/zlh/Desktop/petalinux_706/build/tmp/work/plnx_zynq7-xilinx-linux-gnueabi/device-tree/xilinx+gitAUTOINC+b7466bbeee-r0 -o ${DTS_NAME}.dtb `basename ${DTS_FILE}`.pp'
| ERROR: Function failed: do_compile (log file is located at /home/zlh/Desktop/petalinux_706/build/tmp/work/plnx_zynq7-xilinx-linux-gnueabi/device-tree/xilinx+gitAUTOINC+b7466bbeee-r0/temp/log.do_compile.33532)
ERROR: Task (/home/zlh/Desktop/petalinux/components/yocto/source/arm/layers/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/device-tree.bb:do_compile) failed with exit code '1'
NOTE: Tasks Summary: Attempted 2299 tasks of which 2295 didn't need to be rerun and 1 failed.

Summary: 1 task failed:
/home/zlh/Desktop/petalinux/components/yocto/source/arm/layers/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/device-tree.bb:do_compile
Summary: There was 1 ERROR message shown, returning a non-zero exit code.
ERROR: Failed to build project

and the pl.dtsi file

*
* CAUTION: This file is automatically generated by Xilinx.
* Version:
* Today is: Mon Aug 24 06:45:06 2020
*/


/ {
amba_pl: amba_pl {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges ;
axi_adrv9009_rx_clkgen: axi_clkgen@43c10000 {
clock-names = "clk", "s_axi_aclk";
clocks = <&misc_clk_0>, <&clkc 15>;
compatible = "xlnx,axi-clkgen-1.0";
reg = <0x43c10000 0x10000>;
};
misc_clk_0: misc_clk_0 {
#clock-cells = <0>;
clock-frequency = <100000000>;
compatible = "fixed-clock";
};
axi_adrv9009_rx_dma: axi_dmac@7c400000 {
clock-names = "s_axi_aclk", "m_dest_axi_aclk", "fifo_wr_clk";
clocks = <&clkc 15>, <&clkc 16>, <&misc_clk_1>;
compatible = "xlnx,axi-dmac-1.0";
interrupt-names = "irq";
interrupt-parent = <&intc>;
interrupts = <0 31 4>;
reg = <0x7c400000 0x1000>;
};
misc_clk_1: misc_clk_1 {
#clock-cells = <0>;
clock-frequency = <100000000.0>;
compatible = "fixed-clock";
};
axi_adrv9009_rx_jesd_rx_axi: axi_jesd204_rx@44aa0000 {
clock-names = "s_axi_aclk", "core_clk";
clocks = <&clkc 15>, <&misc_clk_1>;
compatible = "xlnx,axi-jesd204-rx-1.0";
interrupt-names = "irq";
interrupt-parent = <&intc>;
interrupts = <0 34 4>;
reg = <0x44aa0000 0x4000>;
};
axi_adrv9009_rx_os_clkgen: axi_clkgen@43c20000 {
clock-names = "clk", "s_axi_aclk";
clocks = <&misc_clk_0>, <&clkc 15>;
compatible = "xlnx,axi-clkgen-1.0";
reg = <0x43c20000 0x10000>;
};
axi_adrv9009_rx_os_dma: axi_dmac@7c440000 {
clock-names = "s_axi_aclk", "m_dest_axi_aclk", "fifo_wr_clk";
clocks = <&clkc 15>, <&clkc 16>, <&misc_clk_1>;
compatible = "xlnx,axi-dmac-1.0";
interrupt-names = "irq";
interrupt-parent = <&intc>;
interrupts = <0 33 4>;
reg = <0x7c440000 0x1000>;
};
axi_adrv9009_rx_os_jesd_rx_axi: axi_jesd204_rx@44ab0000 {
clock-names = "s_axi_aclk", "core_clk";
clocks = <&clkc 15>, <&misc_clk_1>;
compatible = "xlnx,axi-jesd204-rx-1.0";
interrupt-names = "irq";
interrupt-parent = <&intc>;
interrupts = <0 36 4>;
reg = <0x44ab0000 0x4000>;
};
axi_adrv9009_rx_os_xcvr: axi_adxcvr@44a50000 {
clock-names = "s_axi_aclk";
clocks = <&clkc 15>;
compatible = "xlnx,axi-adxcvr-1.0";
reg = <0x44a50000 0x10000>;
};
axi_adrv9009_rx_xcvr: axi_adxcvr@44a60000 {
clock-names = "s_axi_aclk";
clocks = <&clkc 15>;
compatible = "xlnx,axi-adxcvr-1.0";
reg = <0x44a60000 0x10000>;
};
axi_adrv9009_tx_clkgen: axi_clkgen@43c00000 {
clock-names = "clk", "s_axi_aclk";
clocks = <&misc_clk_0>, <&clkc 15>;
compatible = "xlnx,axi-clkgen-1.0";
reg = <0x43c00000 0x10000>;
};
axi_adrv9009_tx_dma: axi_dmac@7c420000 {
clock-names = "s_axi_aclk", "m_src_axi_aclk", "m_axis_aclk";
clocks = <&clkc 15>, <&clkc 16>, <&clkc 16>;
compatible = "xlnx,axi-dmac-1.0";
interrupt-names = "irq";
interrupt-parent = <&intc>;
interrupts = <0 32 4>;
reg = <0x7c420000 0x1000>;
};
axi_adrv9009_tx_jesd_tx_axi: axi_jesd204_tx@44a90000 {
clock-names = "s_axi_aclk", "core_clk";
clocks = <&clkc 15>, <&misc_clk_1>;
compatible = "xlnx,axi-jesd204-tx-1.0";
interrupt-names = "irq";
interrupt-parent = <&intc>;
interrupts = <0 35 4>;
reg = <0x44a90000 0x4000>;
};
axi_adrv9009_tx_xcvr: axi_adxcvr@44a80000 {
clock-names = "s_axi_aclk";
clocks = <&clkc 15>;
compatible = "xlnx,axi-adxcvr-1.0";
reg = <0x44a80000 0x10000>;
};
axi_hdmi_clkgen: axi_clkgen@79000000 {
clock-names = "clk", "s_axi_aclk";
clocks = <&clkc 16>, <&clkc 15>;
compatible = "xlnx,axi-clkgen-1.0";
reg = <0x79000000 0x10000>;
};
axi_hdmi_core: axi_hdmi_tx@70e00000 {
clock-names = "hdmi_clk", "vdma_clk", "s_axi_aclk";
clocks = <&misc_clk_2>, <&clkc 15>, <&clkc 15>;
compatible = "xlnx,axi-hdmi-tx-1.0";
reg = <0x70e00000 0x10000>;
};
misc_clk_2: misc_clk_2 {
#clock-cells = <0>;
clock-frequency = <148484848.4848485>;
compatible = "fixed-clock";
};
axi_hdmi_dma: axi_dmac@43000000 {
clock-names = "s_axi_aclk", "m_src_axi_aclk", "m_axis_aclk";
clocks = <&clkc 15>, <&clkc 15>, <&clkc 15>;
compatible = "xlnx,axi-dmac-1.0";
interrupt-names = "irq";
interrupt-parent = <&intc>;
interrupts = <0 29 4>;
reg = <0x43000000 0x1000>;
};
axi_iic_main: i2c@41600000 {
#address-cells = <1>;
#size-cells = <0>;
clock-names = "s_axi_aclk";
clocks = <&clkc 15>;
compatible = "xlnx,axi-iic-2.0", "xlnx,xps-iic-2.00.a";
interrupt-names = "iic2intc_irpt";
interrupt-parent = <&intc>;
interrupts = <0 30 4>;
reg = <0x41600000 0x1000>;
};
axi_spdif_tx_core: axi_spdif_tx@75c00000 {
clock-names = "spdif_data_clk", "s_axi_aclk", "dma_req_aclk";
clocks = <&misc_clk_3>, <&clkc 15>, <&clkc 15>;
compatible = "xlnx,axi-spdif-tx-1.0";
reg = <0x75c00000 0x10000>;
};
misc_clk_3: misc_clk_3 {
#clock-cells = <0>;
clock-frequency = <12287988>;
compatible = "fixed-clock";
};
axi_sysid_0: axi_sysid@45000000 {
clock-names = "s_axi_aclk";
clocks = <&clkc 15>;
compatible = "xlnx,axi-sysid-1.0";
reg = <0x45000000 0x10000>;
};
rx_adrv9009_tpl_core_tpl_core: ad_ip_jesd204_tpl_adc@44a00000 {
clock-names = "link_clk", "s_axi_aclk";
clocks = <&misc_clk_1>, <&clkc 15>;
compatible = "xlnx,ad-ip-jesd204-tpl-adc-1.0";
reg = <0x44a00000 0x1000>;
};
rx_os_adrv9009_tpl_core_tpl_core: ad_ip_jesd204_tpl_adc@44a08000 {
clock-names = "link_clk", "s_axi_aclk";
clocks = <&misc_clk_1>, <&clkc 15>;
compatible = "xlnx,ad-ip-jesd204-tpl-adc-1.0";
reg = <0x44a08000 0x1000>;
};
tx_adrv9009_tpl_core_tpl_core: ad_ip_jesd204_tpl_dac@44a04000 {
clock-names = "link_clk", "s_axi_aclk";
clocks = <&misc_clk_1>, <&clkc 15>;
compatible = "xlnx,ad-ip-jesd204-tpl-dac-1.0";
reg = <0x44a04000 0x1000>;
};
};
};