I'm moving this thread to the FPGA reference design sub-community. -- Actually I don't have right to do that. Please open up a new thread with your issue at FPGA reference design.
In order to help you, you need to describe exactly what is your problem.
I am sorry my problem description was misleading. I want to modify the reference design of the daq2 with ZC706 so I can transmit sin wave through the DAC using hdl (dds compiler ip). However, the output is totaly destorted.
Please open a new thread here: https://ez.analog.com/fpga