How to synchronize SPI clock to system clock to achieve maximum SPI data rate on the TMC5160?

The TMC5160's maximum SPI data rate when using an external clock is 1/2 of the system clock (CLK).

However, in order to achieve these high data rates, the SPI clock (SCK) must be synchronized to the system clock.  This article intends to clarify these requirements, since the datasheet provides little information on what this synchronization means in practice.

 

SCK and CSN are sampled in the IC with rising edge of CLK. The SCK signal must be sampled once as a “0” and once as a “1”. To achieve that, SCK frequency must be beneath fCLK/2 and the SCK signal must have a valid value (either 0 or 1) when the rising edge of CLK occurs. As such, it is helpful if SCK changes states during the falling edge of CLK, so that the SCK signal is stable upon the CLK rising edge. 

Now we look at the Chip specific properties:
The CLK Signal is not filtered.
SPI signals are filtered with a bandwidth of 20ns ± 40%, which is 12-28ns.
CLK is unfiltered, but the CLK tree needs longer than normal inputs (3-10ns). As a result, SCK should not change 2-25ns before the rising edge on CLK.
 

Conclusion: In order to achieve maximum SPI speed, the SPI signals should be synced to the falling edge of CLK. Changes in SCK 2-25ns before the rising edge of CLK should be avoided as well.