Q. Can the I2S bit clock be used with the internal PLL to generate the master clock, and therefore no external master clock source would be needed?
A. The user will always need to supply a master clock (MCLK) input to the part. The PLL referred to is an internal digital PLL, not an analog PLL.
If they are using the interface in slave mode (providing the BCLK and LRCLK inputs), and if BCLK happens to be > 10MHz, then there shouldn’t be any issue with having to provide a separate MCLK, but the part is not able to generate an MCLK from the BCLK.
Now, the MCLK can be any frequency clock >10MHz, and it may be asynchronous and unrelated to the LRCLK and BCLK frequencies. They can use any frequency MCLK present in their system to get the part to function in either slave or master modes of operation.