Question
1. Amplifier noise figure against frequencyNoise Figure data does not yet exist.2. Amplifier Psat against frequency rather than typical valuesThe validation data we collect is taken on such a limited number of samples that it would not be statistically sound to try to use it to describepart-to-part variation.Our production test data is the only data we’d have available that I consider statistically relevant for describing part-to-part variation. Even thatdata, unless acquired across multiple production lots, might not give an accurate picture of the type of variation you could see from productionparts. This is humongous data that we have to collect to suffice this question. The only parameters we truly guarantee are the ones having with Minor Max specifications on the Electrical Specifications table.3. Power Supply Voltage to Insertion Phase conversion factors, °/V, for both Gate and Drain supplies.Though this is not in the data sheet, it could be obtained from S-parameter data we’ve already taken over Vdd (20, 25, 28, and 32V) and Iddq (100,150, 225, and 300 mA).4. Power Supply Voltage to Gain or Power out conversion factors, dB/V, for both Gate and Drain supplies. Though this is not in the data sheet, itcould be obtained from Power data we’ve already taken over Vdd (20, 25, 28, and 32V) and Iddq (100, 150, 225, and 300 mA).5. Do the Vdd1 and Vdd2 drain voltages control different stages within the amplifier and if so can these be controlled separately to minimise outputnoise when the Amplifier is not required to provide output signal. For example it might be convenient to set VDD1 to 0V in order to reduce outputnoise, when the Amplifier is not required to produce output signal, while leaving VDD2 powered up. While, presumably, this would not reduce theAmplifier output noise as much as removing VDD2, it could be more convenient, from the power supply point of view, to switch the VDD1 supply between0V and 28V - rather than the VDD2 supply, where the current demand may be higher.That is correct. The part has two gain stages in cascade. The two stages can be biased together or separately. In the typical application, Vdd1 andVdd2 are connected together and biased simultaneously. Likewise with Vgg1 and Vgg2. The typical application is reflected on the EVB where Vdd1 andVdd2 are bussed together, while Vgg1 and Vgg2 are bussed together. However, please notice that Vdd1 and Vdd2 are capacitively bypassed separatelyfrom one other, as are Vgg1 and Vgg2. The individual bypassing might be important for performance and/or stability. I’m aware of no reason why thetwo stages should not be biased separately.
6. In order to reduce Amplifier output noise, for periods of operation where the Amplifier output signal is not required, a potentially attractiveapproach might seem to be:set the Gate Bias Voltage(s) to a negative voltage that will cause Amplifier stages to minimal Quiescent Current, while leaving the VDD1 and VDD2supplies powered up.However, use of negative bias, to reduce Amplifier Gain, has a very bad track record with GaAs devices where device destruction can, for reasons thatare not clear to the author, result.If you mean negative gate bias, I’m not aware of a bad track record of reliability. The production tests for manyof our GaAs power amps apply the fully Vdd while pulsing the gate bias so as to toggle between pinch-off and the nominal target bias. Doing soduty-cycles the DC bias, which reduces the average Pdiss and makes operation in a socket (where there is little thermal relief) safe. Can GateVoltage be used to reduce the HMC1114 Gain for periods when signal from the HMC1114 is not required, without seriously decreasing the life of thedevice? Yes. For information: in the Radar application it might be required to use the Amplifier with a few % to 50% duty cycle for pulses from100ns to 10ms, with the requirement to reduce the HMC1114 output noise between pulses by 20dB or more.We have not evaluated the part in this manner, so I don’t know how much noise reduction you can expect. I recommend that you start with the stock EVBand modify it in a way that will allow them to evaluate the gate-pulsed performance using their target periods and pulse widths to ensure that theperformance is adequate. To do so you would need to separate Vgg1 from Vgg2 by cutting a trace, and make provisions to input a separate signal foreach gate. That could be done by soldering coaxial “pig tails” to each of the gate signal traces. From there you can make adjustments to the gatebypass capacitances, if required to achieve the transient performance required.7. Questions 5 and 6 are motivated by the need to reduce HMC1114 output noise, by 20dB, for periods where output signal is not required. From ourpoint of view, a high power switch on the Amplifier output is an inconvenient way to reduce the Amplifier output Noise, so if Analog Devices cansuggest a convenient way(s) to reduce the output noise of the HMC1114, when output signal is not required from the HMC1114, then this would begreatly appreciated. I think that the pulsed-gate bias approach described above is the best and most easily implemented approach that would notrequire the use of high power, high isolation switches.8. I assume that if Vdd1 and Vdd2 are separate controls then the same would be true of the Vgg1 and Vgg2 inputs? For proper operation each stageneeds to be biased, though each stage does not need to be biased separately; the two stages can be biased either together or separately. Vgg1 andVdd1 provide gate and drain bias to gain stage 1, while Vgg2 and Vdd2 provide gate and drain bias to gain stage 2. Inside the package and on the die,Vdd1 is independent of Vdd2 and Vgg1 is independent of Vgg2. Please note that the stock EVB does not provide for separate biasing.9. Has a maximum, Survival, negative Gate Bias Voltage been determined, as yet? Yes. Vgg1 and Vgg2 AMRs are -8 Vdc. Such info will likely be includedin any data sheet update.10. A set of Capacitors has been recommended for Drain and Gate Power Supply decoupling in the information about the Evaluation PCB. However,depending on exactly which Capacitors are fitted, the impedance seen looking out of the HMC1114 VDD and VG pins can vary considerably as a functionof frequency. Please can Analog Devices supply recommendations about the impedance vs frequency that should be seen looking out of the variousHMC1114 VDD and VG pins in order to ensure proper device operation? Maybe the frequency range of interest could be from VLF? to 10GHz? or more? Iexpect you should look low-Z in-band, but I’m not sure if there are any recommendations out-of-band. I’ve asked Design to comment and will reply onceI’ve received their input.
11. Is there any measured data for the residual phase noise of this amplifier? No12. Is there any measured data for the residual amplitude noise of this amplifier? No13. Is there any measured AM to PM conversion data, deg/dB? No14. Is there any set-up procedures available for this amplifier in terms of gate bias?Bias Sequence section of the following application note:
http://www.analog.com/media/en/technical-documentation/application-notes/mmic_amplifier_biasing_procedure.pdf
In general, the gates should always be biased to a voltage that will not result in excessive Idd upon application of Vdd. If the gates are left openor if the gate voltage is too positive upon application of Vdd, then excessive Idd and Pdiss could damage the part. Though not required, typicaloperation would have Vgg1 connected to Vgg2, and Vdd1 connected to Vdd2. That would allow the gates to be controlled together, and the drains to becontrolled together. More negative gate voltages result in lower drain currents, while more positive gate voltages result in higher drain currents.
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