Question
We are using a couple of AD9850 DDS's on one of our boards.
I am using the serial interface to regulate the output frequency
relative to the input frequency to which the DDS is locked to.
1st question: Is it possible to increase AND decrease the
output frequency of the DDS relative to its input frequency?
We initially use word "0009BA3C00" and a 77.76MHz input reference.
If yes, how? Please provide and Incr and Decr example using
the word above.
2nd question: What is the response time of the DDS in order
to achieve the new initialised output frequency?
3th question: Is this response time a function of the
size of the increment and decrement step variation?
Answer
In general, Direct Digital Synthesis (DDS) uses a crystal oscillator, Sine or
Cosine lookup table, some digital logic and a high AC performance DAC to
directly generate sine and cosine signals with of arbitrary frequency and
phase. All of the signal generation and processing is performed in the digital
domain and the high performance DAC does the conversion to the analog domain.
Because the signal is generated digitally, the phase and frequency are very
accurate (frequency resolution of 0.001Hz) and can be changed very rapidly
without the inherent lock-time required by a PLL solution.
On the AD9850, you do not increment and decrement the output frequency as such,
instead you simply load in a new frequency tuning word and the DAC starts to
output the new frequency immediately after a delay of 18 clock cycles.
Programming the AD9850 is described on page 9 of the datasheet. The AD9850
requires 5 byte writes to update the frequency register, this takes 5 x 7ns =
35ns. The latency between updating the frequency register and the output
frequency appearing at the output is 18 reference clock cycles. With a 50MHz
clock, the latency is 18 x 20ns = 360ns. In theory you can update the output
frequency in 360ns + 35ns = 395ns. In practice, you will be limited by the
speed of your digital interface.
Whether you are using serial or parallel programming, a complete 40bit word
must be written to the AD9850 each time the frequency register is modified.
In practice you can a DDS can be used to generate frequency up to approximately
one third of the input reference frequency. As you increase the output
frequency further, the filter requirements become prohibitive and the SNR and
THD start to degrade.
Not quite sure what type of example you are looking for. A master clock
frequency of 77.76MHz and tuning word of 0009BA3C00H ( 163200000 in decimal )
produces an output frequency of (163200000 x 77760000 ) / 2^32 = 2.95MHz.
To increment and decrement the output frequency simply use the formula
Frequency Tuning Word = ( Output Frequency x 2^32 ) / Input Clock Frequency
