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Questions about AD74413R datasheet

Category: Datasheet/Specs
Product Number: AD74413R

Hello!

I am reading the AD74413R datasheet and I have thee following questions:

  1. On page 61, the datasheet says that “the user must wait 100 µs before starting conversions”. Is that 100 µs after turning on the ADC by writing 01h to the CONV_SEQ bits? or is it a waiting time between consecutive single sequence conversions?
  2. On page 61, it is not clear whether after writing mode 01h to the CONV_SEQ bits for the first time (by turning on the ADC) the single conversion will be performed after the ADC is fully turned on or on the contrary it is necessary to write mode 01h again to perform the conversion.
  3. On page 61, where the ADC conversion modes are described, it says that if 01h (single sequence conversion) is written to the CONV_SEQ bits of the ADC_CONV_CTRL register, the ADC will turn on if it is off. When mode 10h (continuous conversion) is written, will the ADC also turn on if it is off? Reading the description of that mode I understand first I have that I have to set the 01h mode in CONV_SEQ to turn on the ADC and then, set the 10h in CONV_SEQ to start the continuous conversion mode. Maybe it is a mistake in the datasheet?

  4. On page 66, the description of the LIVE STATUS register says that the bits in that register are not latched (except bit 14, ADC_DATA_RDY, which appears to be latched). I assume, by opposition, that all bits of the ALERT STATUS register (pages 64 and 65) are latched, not just RESET_OCCURRED (bit 15) and CAL_MEM_ERR (bit 14). Is this correct?
  5. On pages 62 and 63, the datasheet says that the DIAG0_ASSIGN bits "Selects the diagnostic assigned to the DIAG_RESULTx registers, Bit 0". I don't understand what "Bit 0" means in that phrase. I think that DIAG0_ASSIGN bits configure what kind of diagnosis behavior will be assigned to the Diagnosis Channel 0, and the result of the diagnosis process will be available at DIAG_RESULT0 register.
  6. On pages 62 and 63, the datasheet says that the DIAG0_ASSIGN bits “Selects the diagnosis assigned to the DIAG_RESULTx registers, Bit 0”. I don't understand what “Bit 0” means in that sentence. As I understand it is that the DIAG0_ASSIGN bits configure what type of diagnostic function will be assigned to Diagnostic Channel 0, and the result of the diagnostic process of this channel will be available in the DIAG_RESULT0 register.
  7. On page 64, the description of the CAL_MEM_ERR bit seems to be incomplete and I find it a bit confusing. How are you supposed to know that the internal memory calibration is complete if you can't write any registers via SPI until the calibration is complete? Because the nALERT pin will be asserted after a reset, so you can't discriminate if the device is ready by waiting for the nALERT pin to be high (disabled).
  8. On pages 52 and 68: being AUTO_RD_EN=1h and SPI_RD_RET_INFO=0h, if I set, for example, address 0x00 in the READBACK_ADDR and perform consecutive WRITE to different registers will the AD74413 return by SDO address 0x00 and its contents on the first write, address 0x01 and its contents on the second write, and so on, or will it always return the same address (0x00) and its contents? I assume that Streaming Mode only works after a 2-stage readback process, but I don't know if that behavior holds for write operations when AUTO_RD_EN=1h.
  9. On pages 50 and 68: Is the behavior of the AD74413R exactly the same when performing a software reset as when performing a hardware reset?
  10. On page 68: Is the command written to the CMD_KEY register executed after finishing the writing process or do I have to do some extra step?
  • Hi  ,

    thank you for your queries, let me answer them one by one.

    1. Powering up ADC takes 100us, for reason, there is delay needed. There is no need for delay between consecutive single sequence conversions. 

    2. When CONV_SEQ = 0b11 (ADC is powered down) and user set CONV_SEQ = 0b01 it will start single sequence conversion (will perform one conversion). 

    3. You are right it is DS typo and 0b10 should read 0b01. (It will be address in following revision of the DS.)

    4. You are correct that LIVE_STATUS bits are not latched (except ADC_DATA_RDY). Live status should indicate currently active errors. ALERT_STATUS is showing errors which occured in past, all of the bits are latched, including RESET_OCCURED (indicates that reset have been performed, note that sometimes DUT reset due to thermal shutdown or under voltage scenario) and CAL_MEM_ERR. Good guidance is, that bits with Access "R" Read only are not latched and with "R/W1C" are latched.

    5. and 6. You are absolutely correct about described behavior. "I think that DIAG0_ASSIGN bits configure what kind of diagnosis behavior will be assigned to the Diagnosis Channel 0, and the result of the diagnosis process will be available at DIAG_RESULT0 register." There is not more to it. Perhaps "Bit 0" is bit unfortunate indication, where to find resulting data.

    7. You are right, it might be challenging to understand based on the description. In short after power up (After AVDD and DVCC power up), you should wait typ. 10ms, this will ensure that CAL memory will be fully refreshed, do not perform any SPI writes. However, when for example DUT is reset due to low voltage and eventually powered up again, it may cause the situation that MCU will be powered up and attempting the SPI writes. In such case CAL_MEM_ERR will assert. 

    8. When Auto Read is enabled, and you perform single SPI transaction (write to any address), SDO will output data of the register address defined in the READBACK_ADDR. It will keep outputting same data with each write, until you change READBACK_ADDRESS or will hold SYNC low for "Streaming mode. In short it always return same address, unless you change it or use "streaming mode". As per Datasheet, streaming mode is available also in Auto Readback (see page 53. Auto Readback section (last sentence). 

    9. SW vs HW reset: Let me double check with design and follow-up on the same.

    10.  Command will be executed automatically after writing required key or sequence of keys. (No need for step.)

    Regards,

    Arnost

  • Hi APavllk,

    Thank you very much for your answers, I think it is almost all clear now. Let me ask you again just to clarify some aspects:

    2. When CONV_SEQ = 0b11 (ADC is powered down) and user set CONV_SEQ = 0b01 it will start single sequence conversion (will perform one conversion). 

    And as you say in your first answer, the first time I set CONV_SEQ = 0b01 (turning on ADC + simple conversion) the MCU should wait ~100us before reading the CH_ADC_RESULTx or DIAG_RESULTx registers. Am I right?

    4. You are correct that LIVE_STATUS bits are not latched (except ADC_DATA_RDY). Live status should indicate currently active errors. ALERT_STATUS is showing errors which occured in past, all of the bits are latched, including RESET_OCCURED (indicates that reset have been performed, note that sometimes DUT reset due to thermal shutdown or under voltage scenario) and CAL_MEM_ERR. Good guidance is, that bits with Access "R" Read only are not latched and with "R/W1C" are latched.

    Yes, I assumed that bits with “R” access did not latch and those with “R/W1C” access did, but I wanted to be sure. Thank you.

    9. SW vs HW reset: Let me double check with design and follow-up on the same.

    Okay, I will wait for your response.

    Finally, I have another question that I forgot to consult last time:

    11. On page 60, there is a note in the description of I_LIMIT that says “the VOUT sink current limit is normally set to 4.5 mA”. I don't understand what this means, because it is in the description of the I_LIMIT bit that allows you to set the source current limit of channels A-D, between 7.5 mA and 30 mA. Could you explain me what that 4.5 mA limit means?

    Thank you very much.

    Regards,

    Rafa.

  • Hi  ,

    sure no problem, let's clarify remaining questions.

    2. When CONV_SEQ = 0b11 (ADC is powered down) and user set CONV_SEQ = 0b01 it will start single sequence conversion (will perform one conversion). 

    CH_ADC_RESULTx or DIAG_RESULTx can be read as soon as data are available (even, before "new" data are available), this does not affect the ADC functionality. Point which is being communicated in the datasheet is, that once the ADC requires power up (no in idle stage), additional 100us is needed, before conversion takes place. 

    4. You are correct that LIVE_STATUS bits are not latched (except ADC_DATA_RDY). Live status should indicate currently active errors. ALERT_STATUS is showing errors which occured in past, all of the bits are latched, including RESET_OCCURED (indicates that reset have been performed, note that sometimes DUT reset due to thermal shutdown or under voltage scenario) and CAL_MEM_ERR. Good guidance is, that bits with Access "R" Read only are not latched and with "R/W1C" are latched.

    Yes, I assumed that bits with “R” access did not latch and those with “R/W1C” access did, but I wanted to be sure. Thank you.

    I agree, always better to confirm, than assume. I am happy, this topic is cleared. 

    9. SW vs HW reset: Let me double check with design and follow-up on the same.
    Okay, I will wait for your response.

    I have confirmation from digital design, functionality of the SW and HW reset is the same. These resets have identically functionality and outcome. (Behavior is the same when performing HW (/reset pin) and SW (CMD keys) reset.)

    11. On page 60, there is a note in the description of I_LIMIT that says “the VOUT sink current limit is normally set to 4.5 mA”. I don't understand what this means, because it is in the description of the I_LIMIT bit that allows you to set the source current limit of channels A-D, between 7.5 mA and 30 mA. Could you explain me what that 4.5 mA limit means?

    You are correct, I_LIMIT affect the range of the limit of current which is allowed to be sourced in Vout mode. Additional note about 4.5mA is, that beside sourcing current limit, Vout have also sinking current limit (capability). Sinking current limit is not possible to program or adjust and it is always "typically 4.5mA". This means, in Vout mode, screw terminal voltage can be regulated also with capability of sinking little amount of the current (4.5mA), to ensure, that output voltage is desired value. 

    Let me know, if I have cleared all your questions.  

    Regards,

    Arnost

  • Hello again Apavlik,

    CH_ADC_RESULTx or DIAG_RESULTx can be read as soon as data are available (even, before "new" data are available), this does not affect the ADC functionality. Point which is being communicated in the datasheet is, that once the ADC requires power up (no in idle stage), additional 100us is needed, before conversion takes place. 

    I guess I didn't explain myself well enough, but anyway, you answered my question, so thank you!

    I have confirmation from digital design, functionality of the SW and HW reset is the same. These resets have identically functionality and outcome. (Behavior is the same when performing HW (/reset pin) and SW (CMD keys) reset.)

    Ok, perfect, thank you very much for the confirmation.

    You are correct, I_LIMIT affect the range of the limit of current which is allowed to be sourced in Vout mode. Additional note about 4.5mA is, that beside sourcing current limit, Vout have also sinking current limit (capability). Sinking current limit is not possible to program or adjust and it is always "typically 4.5mA". This means, in Vout mode, screw terminal voltage can be regulated also with capability of sinking little amount of the current (4.5mA), to ensure, that output voltage is desired value. 

    Well, everything is clear.

    Thank you very much for your answers.