SPI Readback Mode timing diagram of the AD74413R

Question

Hello!

I am reading the AD74413R datasheet and on page 52 it explains the Readback Mode. I don't understand how SCLK and nSYNC pins work in that mode, because figure 57 shows SCLK acting as a kind of Chip Select while the nSYNC pin is acting as SCLK. could you give me some details about that mode? Maybe it is a typo in the datasheet and where it says nSYNC should be SCLK and vice versa.

APavlik · Accepted Answer

Hi rafaelsf , 
 you are right, figure is typo in the datasheet, which will be fixed with version update. Thank you for pointing it out. 
 /SYNC and SCLK labels are swapped. AD74412R datasheet have signals labeled correctly.

Regards, 
 Arnost)

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SPI Readback Mode timing diagram of the AD74413R