HIGH LIMIT 1 (PAGE 0x05) Registers Settings

Hi junboyi@bluedanube.com ,

thank you for your question, please refer to the AD7293 datasheet (DS), "Internal Channel Monitoring" section, which describes scaling of each of the mentioned channels. (Fugure 42. attached for your convenience, which reflects the same, more detaild description is in DS.) Resulting codes are then compared to determine, if ALERT will be triggered based on the configured limit. 

Regards,

Arnost

If I need to figure out how to map the input to Limit Register ADC data, then I don't need to ask questions here.

As user, I would like to have a simple, direct conversion between input voltage range to Mux range, especially for those with negative voltage range.

Thanks.

JYI

Yes, the host controller needs to know what is happening when alert is noticed even the alert condition is gone.

I understand that setting Hysteresis to maximum will keep the alert status registers un-reset. My question is when set the maximum of Hysteresis to ADC maximum 0xFFF, it doesn't work like that way, but 0x7FF does based on my testing for VIN0 and BI-VOUT0 background monitoring functionality.

For the alert asserted timing, only VIN0 is enabled on the background for my testing. The measurement is from VIN0 input over high limit setting to Alert 0 Pin asserted (Active LOW), that took about 320-micro-second which is much longer than it supposed to be based on the DS ADC conversion timing.

Thanks.

JYI

HI JYI,

I was investigating your query concerning the 0x7FF and 0xFFF hysteresis code, unfortunately it takes much longer, than I expected and it is still under investigation. I was able to replicate the same and what you results indicates so far (if that is any help to you), in case of LOW limit, once the total value of hysteresis and low limit setting is above 6144, circuit does not behave as expected (tested at Vin0 and Vin2). 

I need to investigate more, to give you more insights and recommendations.

Regards,

Arnost

Two testing for Alert timing have been carried out and the results are not understood.

Scenario 1, Only IS-0 background is enabled.

IS-0: High Limit=100mA, UNI-DAC-0=1.5V for Clamping Referencing. From IS-0 Jump to 160mA to Alert-0 Pin asserted took about 1000uS.

Scenario 2, Only VIN-0 background is enabled, UNI-DAC-0 as input source.

Test-1: VIN-0 High Limit=2.0V, Hysteresis=0.

A: VIN-0=0V Jumping to 2.5V, Alert-0 Pin Asserted => UNI-DAC-0 Clamped(0V) Period: 280uS. 

B: VIN-0=1.5V Jumping to 2.5V, Alert-0 Pin Asserted => UNI-DAC-0 Clamped(0V) Period: 150uS. 

C: During Alert-0 Pin Asserted and Deserted repeat cycling (Snooze Disabled), Asserted Period: 4uS, Deserted Period: 10uS.

Test-2: VIN-0 High Limit=2.0V, Hysteresis=0.2V.

Situation A and B are the same as Test-1 A and B. 

C: During Alert-0 Pin Asserted and Deserted repeat cycling (Snooze Disabled), Asserted Period: 20uS, Deserted Period: 60uS.

From the testing above, not understanding why it takes so long to trigger the alert for both scenarios? and for Test-2, why the initial setting (0V verse 1.5V) effects the Alert Asserted timing period, why the Hysteresis setting effects the Asserted and Deserted period and why the Asserted period is much shorter than Deserted period for Asserted-Deserted cycling?

Some screen shots are captured.

JYI

Hi JYI,

Scenario 1: Could you clarify what is the GAIN setting and value of the sense resistor used. Gain setting impacts integration time in case of monitoring IS0. 

Scenario 2: Could you clarify what UNI-DAC-0 as input means, is output of the DAC connected at VIN0? 

I have done experiment with External Generator at VIN0 (Green signal) and monitoring Alert0/GPIO3 output pin and it looks to me reasonably spread around 2.3us as per datasheet. 

Time between asserting and de-asserting ALERT0 pin, do you have in mind, it is open collector? What value of pull up are you using? 

This might not be entire reason for the difference but perhaps might contribute. 

Regards,

Arnost

The test is based on ADI EVAL-AD7293SDZ board. There is a pull-up R98(10K) and pull-down R73(2K) with LED(D6) on GPIO3.

For Scenario 1, gain (6.25), open-loop and Rsense=0.442(ohm).

For Scenario 2, the UNI-DAC0 output is as VIN0 input source, so the clamping can be seen.

Removing the Closed-Loop Daughter board from EVAL-AD7293SDZ board and repeat the same tests shows the same results.

If you carried out your testing based on EVAL-AD7293SDZ board also, may be missing hardware setting for EVAL-AD7293SDZ board for my testing because my testing didn't get the same timing result as yours.

Chn-3(Pink): Alert-0 Pin, Active LOW.
Chn-4(Green): RS0+.
Chn-2(Blue):UNI-DAC0(Clamping Reference).
Gain=6.25, Open-loop, Rsense=0.442(ohm).
IS0: High Limit=100mA, Low Limit=0.
Turn-on DC Switch => IS0 => 150mA => Alert 0 Pin Asserted => UNI-DAC0 => 0V.
IS0 Jump High to Alert 0 Pin Asserted: 1mS.

Chn-3(Pink): Alert-0 Pin, Active LOW.
Chn-4(Green): VIN-0 Driven By UNI-DAC-0.
VIN-0: High Limit=2.0V, Hysteresis=0V.
VIN-0 => 0V => 2.5V => Alert-0 Pin Asserted => UNI-DAC-0 Clamped(0V).
VIN-0 Jump High to Alert 0 Pin Asserted Period: 280uS.

Chn-3(Pink): Alert-0 Pin, Active LOW.
Chn-4(Green): VIN-0 Driven By UNI-DAC-0.
VIN-0: High Limit=2.0V, Hysteresis=0V.
VIN-0 => 1.5V => 2.5V => Alert-0 Pin Asserted => UNI-DAC-0 Clamped(0V).
VIN-0 Jump High to Alert-0 Pin Asserted Period: 150uS.

JYI

Disable VIN-0 and IS-0 filters and repeating test got the different results.

VIN-0: 0V => 2.5V, Alert-0 Pin Asserted latency=4uS; 

VIN-0: 1.5V => 2.5V, Alert-0 Pin Asserted latency=5uS; and

IS-0: 0mA => 150mA, Alert-0 Pin Asserted latency=16uS.

Since the filter greatly effects the asserted latency (not sure this is correct), then in what situation, the filter should be turned on?

JYI

There is a little bit confused how to convert required voltage delta, such as 0.5V, to BI-VOUTx Hysteresis Register Code.  

Thanks.

JYI

Hi JYI,

concerning the filter, it is expected, that it affects the "response" to alert, as filtering acts as low pass. (Described at Datasheet Digital Filtering Section.) 

Function of the filter is to reduce "unwanted noise on dc signals", for such reason it should be used, when noise reduction is required by your system at ADC inputs.

Regards,

Arnost

Hi JYI,

concerning the " how to convert required voltage delta, such as 0.5V, to BI-VOUTx Hysteresis Register Code". It would be in principal similar as setting the limit code (asked previously at this thread). 

You can use following formula: 

Absolute range is determined by following table and in BI-VOUTx case is 10V:

Regards,

Arnost

Thanks.

Is it clear for Hysteresis settings 0xFFF0 or 0x7FF0 to keep Alert Pin not reset?

JYI

Thanks.

Is it clear for Hysteresis settings 0xFFF0 or 0x7FF0 to keep Alert Pin not reset?

JYI

How to set target current, such as 10mA, to DAC Input register for close-loop mode?

JYI

Hi JYI,

Here is example, how to set target current in closed loop mode:

The closed loop works as a DAC to define the target current, represented as a voltage, VSET, between 0 V and 1.25 V (This is the value you are setting). A summing node to calculate the difference between the target current and the actual current. So if you wanted 10 mA the current sense voltage would be .01 * 5 = 0.05, multiplied by the gain of 6.25 = 0.3125. Divide that by full scale dac to get fraction = 0.3125/1.25 = 0.25. Multiply that by the full scale ADC code (2 ^ 12) = 1024 => 0x400. So writing 0x400 to the DAC register should set 10mA target current with a 5 ohm sense resistor.

Regards,

Arnost

PS: I apologize Alert Pin Reset is still under investigation. 

Thanks, very helpful.

I am continuing to do testing on EVA board for AD7293 different functionalities for our next design.

Waiting for the Alert Pin Reset is still under investigation outcome.

JYI

Hi JYI,

I apologize, investigation have taken longer, than anticipated. 

I have investigated "Hysteresis settings to keep Alert Pin not reset". 

In case of the High Limit and Hysteresis. Setting [Hysteresis > HighLimit] will result in keeping Alert Pin not reset, until Alert is manually cleared.

However, in case of Low Limit and Hysteresis there is two conditions which needs to be kept:

• 1st condition is setting [Hysteresis > 4095 - LowLimit].
• 2nd condition [6144 >= Hysteresis + LowLimit]  

Keeping this configuration will result in keeping Alert Pin not reset, until Alert is manually cleared.

Because Hysteresis register is shared for LowLimit and HighLimit, optimal configuration needs to be met, to satisfy all condition outlined above. (If Low Limit and High Limit is desired to be used simultaneously.)

Regards,

Arnost

I am redoing the testing relating to Hysteresis setting and Alert reset by BI-VOUT0 channel. The LowLimit=0 (for my understanding is disabled) and no routing to alert.

Test-1: Hysteresis Register=xFFF0 (also tried xFFE0 and x0000, the result is the same as xFFF0). it meets the two conditions as you pointed out. (Hysteresis=4095 >= 4095 - LowLimit) and (Hysteresis + LowLimit <= 6144). Alert Pin is still Set - Reset cycling, see screen shot.

CH1(Yellow): Alert0/Sleep0(External Connected),
CH2(Blue): BI-VOUT0,
CH3(Pink): PA-ON, only controlled By Sleep0,
CH4(Green): RS0+, connected PAVDD controlled by PA-ON.

Test-2: Hysteresis Register=x7FF0 (also tried x8000, the result is the same as x7FF0). it does not meet (Hysteresis=2047 < 4095 - LowLimit) but meets (Hysteresis + LowLimit <= 6144). Alert Pin is keeping asserted as expected. see screen shot.

When Low_Limit=0, Hysteresis=x7FF is still not working as expected, but x7FF does.

JYI

Hi JYI,

I apologies, however I am not able to follow the setting, which you are concerned about.

Can you please provide to me the setting, which I should check in the following format:

RegisterAddress = xxx (Limit setting)

RegisterAddress = xxx (Hysteresis setting)

This will allow me to investigate exactly same setting of concern.  

Regards,

Arnost

Test on BI-Vout0 over high-limit based on the following settings.

Page 0x05(High Limit 1), Register(0x14) = BI-VOUT0MON high limit=x4CC0 (-2.0V),

Page 0x07(Low Limit 1), Register(0x14) = BI-VOUT0MON low limit=x0000,

Page 0x09(Hysteresis 1), Register(0x14) =BI-VOUT0MON hysteresis=0xFFF0 or 0x7FF0.

Also test on IS-0 over high-limit based on the following settings, Gain=6.25, Rsense=0.442,

Page 0x04(High Limit 0), Register(0x28) = ISENSE0 high limit=x9C30 (100mA),

Page 0x06(Low Limit 0), Register(0x28) = ISENSE0 low limit=x0000,

Page 0x08(Hysteresis 0), Register(0x28) =ISENSE0 hysteresis=0xFFF0 or 0x7FF0.

With both ISENSE0 hysteresis settings, Alert Pin is keeping asserted as expected except with 0x7FF0 settings takes a little bit long (about 15uS) to assert the alert pin, see attached screen shots.

IS-0: Hysteresis Reg=xFFF0, Alert latency 60uS.

IS-0: Hysteresis Reg=x7FF0, Alert latency 75uS.

JYI