HIGH LIMIT 1 (PAGE 0x05) Registers Settings

Hi junboyi@bluedanube.com ,

thank you for your question, please refer to the AD7293 datasheet (DS), "Internal Channel Monitoring" section, which describes scaling of each of the mentioned channels. (Fugure 42. attached for your convenience, which reflects the same, more detaild description is in DS.) Resulting codes are then compared to determine, if ALERT will be triggered based on the configured limit. 

Regards,

Arnost

If I need to figure out how to map the input to Limit Register ADC data, then I don't need to ask questions here.

As user, I would like to have a simple, direct conversion between input voltage range to Mux range, especially for those with negative voltage range.

Thanks.

JYI

Hi JYI,

Perhaps I haven't understood you question fully and what you are trying to achieve.

Do you meant, that you want "alert" to be set once triggered, and to stay set even when "fault/out of limits" scenario is no longer present. In such configuration alert will stay set until manually cleared by the user. (by writing 1 to corresponding alert bit).

Such functionality is available at AD7293, you can find it under hysteresis for alerts, program hysteresis to big enough value to corresponding alerts. Perhaps 4096 (full 12-bit range) in your case, and alerts once triggered will stay on, until manually cleared.

Hope this helps. 

Regards,

Arnost 

Thanks for your response.

The description scenario in your email is what I mean exactly.

In our new design with AD7293, the alert pin is routing to sleeping pin to clamp the PA bias when the alert is triggered, such as bias current over driven. But once clamped, the bias current is down to zero, then the alert condition is gone, and the alert registers are reset. As the result, the host controller is unable to know what is happening even though it is noticed via alert signal, such as by interruption. 

This is what I am looking for the solution for this scenario. I will try to use the way you suggested.

JYI

Testing alert functionality on AD7293 EVAL Board according to your suggestion.

Feeding UNI-DACx output to VINx and set VINx High Limit to 2V and VINx Hysteresis to 0xFFF (Register Read as xFFF0).

Set UNI-DACx output to 2.5V -> VINx over High Limit -> Alertx Pin asserted (active LOW) -> UNI-DACx Output 0V (Clamped) -> Alertx Pin LOW last about 50-micro-second -> Alertx Pin deserted (idle HIGH) -> UNI-DACx Output Keeping 0V (Snooze Enabled).

Alerte Summary and Alert Status Reset (Read Register 0x0000).

This result is not what it should be as the one described on your response and is not what I expected.

Is something missing?

Thanks.

JYI

Set Hysteresis x7FF (Register read back x7FF0), not xFFF keeps alert Pin and status registers un-reset even the alert "fault/out of limits" scenario is no longer present. Verified for VINx and BI-VOUTx, but failed to find such as description on data sheet. Not sure it is true for all alerts.

JYI

Measurement of the period from the out of limit to alert pin asserted is about 300 micro-second with only one background channel enabled, such as VIN0. Increasing to two channels double this period.

The ADC sample and conversion period should be less than 15-uS based on the data sheet. The 300-uS from alert condition triggering to alert pin assertion is normal for AD7293 or it can be shorter by the configuration.

What is the fastest alert response timing for AD7293 for single monitoring channel? 

Also, if snoozing disabled, the alert pin asserted period is much shorter than the deserted period. Should these two periods be the same based on ADC sample and conversion time.

JYI

Hi JYI,

I apologies I will need to look into this query and come back to you by end of the week.

Regards,

Arnost

Hi JYI,

my apologies for late answer, I have been looking into your query. Would it be possible to clarify, what mode of operation are you using for initiating a conversion. (As per Datasheet [DS] page 72.) Aren't any other conversions enabled such as Curren Sense monitor or Temperature monitor? 

Typical conversion time in DS for Command mode at Vinx is shorter (~0.7us) than Background Mode (~2.3us).

Knowing your configuration will be appreciated, that will help me to eventually find out, reason for the timing you are indicating. 

I would need to investigate these queries on the bench.

Best regards,

Arnost

Hi JYI,

My apologies, if I haven't expressed myself clearly, my understanding was, that was functionality you were looking for. 

Setting Hysteresis to maximum means, that hysteresis is as big as ADC range, for such reason, it cannot be reset. 

Regards,

Arnost

Yes, the host controller needs to know what is happening when alert is noticed even the alert condition is gone.

I understand that setting Hysteresis to maximum will keep the alert status registers un-reset. My question is when set the maximum of Hysteresis to ADC maximum 0xFFF, it doesn't work like that way, but 0x7FF does based on my testing for VIN0 and BI-VOUT0 background monitoring functionality.

For the alert asserted timing, only VIN0 is enabled on the background for my testing. The measurement is from VIN0 input over high limit setting to Alert 0 Pin asserted (Active LOW), that took about 320-micro-second which is much longer than it supposed to be based on the DS ADC conversion timing.

Thanks.

JYI

HI JYI,

I was investigating your query concerning the 0x7FF and 0xFFF hysteresis code, unfortunately it takes much longer, than I expected and it is still under investigation. I was able to replicate the same and what you results indicates so far (if that is any help to you), in case of LOW limit, once the total value of hysteresis and low limit setting is above 6144, circuit does not behave as expected (tested at Vin0 and Vin2). 

I need to investigate more, to give you more insights and recommendations.

Regards,

Arnost

HI JYI,

I was investigating your query concerning the 0x7FF and 0xFFF hysteresis code, unfortunately it takes much longer, than I expected and it is still under investigation. I was able to replicate the same and what you results indicates so far (if that is any help to you), in case of LOW limit, once the total value of hysteresis and low limit setting is above 6144, circuit does not behave as expected (tested at Vin0 and Vin2). 

I need to investigate more, to give you more insights and recommendations.

Regards,

Arnost

Two testing for Alert timing have been carried out and the results are not understood.

Scenario 1, Only IS-0 background is enabled.

IS-0: High Limit=100mA, UNI-DAC-0=1.5V for Clamping Referencing. From IS-0 Jump to 160mA to Alert-0 Pin asserted took about 1000uS.

Scenario 2, Only VIN-0 background is enabled, UNI-DAC-0 as input source.

Test-1: VIN-0 High Limit=2.0V, Hysteresis=0.

A: VIN-0=0V Jumping to 2.5V, Alert-0 Pin Asserted => UNI-DAC-0 Clamped(0V) Period: 280uS. 

B: VIN-0=1.5V Jumping to 2.5V, Alert-0 Pin Asserted => UNI-DAC-0 Clamped(0V) Period: 150uS. 

C: During Alert-0 Pin Asserted and Deserted repeat cycling (Snooze Disabled), Asserted Period: 4uS, Deserted Period: 10uS.

Test-2: VIN-0 High Limit=2.0V, Hysteresis=0.2V.

Situation A and B are the same as Test-1 A and B. 

C: During Alert-0 Pin Asserted and Deserted repeat cycling (Snooze Disabled), Asserted Period: 20uS, Deserted Period: 60uS.

From the testing above, not understanding why it takes so long to trigger the alert for both scenarios? and for Test-2, why the initial setting (0V verse 1.5V) effects the Alert Asserted timing period, why the Hysteresis setting effects the Asserted and Deserted period and why the Asserted period is much shorter than Deserted period for Asserted-Deserted cycling?

Some screen shots are captured.

JYI

Hi JYI,

Scenario 1: Could you clarify what is the GAIN setting and value of the sense resistor used. Gain setting impacts integration time in case of monitoring IS0. 

Scenario 2: Could you clarify what UNI-DAC-0 as input means, is output of the DAC connected at VIN0? 

I have done experiment with External Generator at VIN0 (Green signal) and monitoring Alert0/GPIO3 output pin and it looks to me reasonably spread around 2.3us as per datasheet. 

Time between asserting and de-asserting ALERT0 pin, do you have in mind, it is open collector? What value of pull up are you using? 

This might not be entire reason for the difference but perhaps might contribute. 

Regards,

Arnost

The test is based on ADI EVAL-AD7293SDZ board. There is a pull-up R98(10K) and pull-down R73(2K) with LED(D6) on GPIO3.

For Scenario 1, gain (6.25), open-loop and Rsense=0.442(ohm).

For Scenario 2, the UNI-DAC0 output is as VIN0 input source, so the clamping can be seen.

Removing the Closed-Loop Daughter board from EVAL-AD7293SDZ board and repeat the same tests shows the same results.

If you carried out your testing based on EVAL-AD7293SDZ board also, may be missing hardware setting for EVAL-AD7293SDZ board for my testing because my testing didn't get the same timing result as yours.

Chn-3(Pink): Alert-0 Pin, Active LOW.
Chn-4(Green): RS0+.
Chn-2(Blue):UNI-DAC0(Clamping Reference).
Gain=6.25, Open-loop, Rsense=0.442(ohm).
IS0: High Limit=100mA, Low Limit=0.
Turn-on DC Switch => IS0 => 150mA => Alert 0 Pin Asserted => UNI-DAC0 => 0V.
IS0 Jump High to Alert 0 Pin Asserted: 1mS.

Chn-3(Pink): Alert-0 Pin, Active LOW.
Chn-4(Green): VIN-0 Driven By UNI-DAC-0.
VIN-0: High Limit=2.0V, Hysteresis=0V.
VIN-0 => 0V => 2.5V => Alert-0 Pin Asserted => UNI-DAC-0 Clamped(0V).
VIN-0 Jump High to Alert 0 Pin Asserted Period: 280uS.

Chn-3(Pink): Alert-0 Pin, Active LOW.
Chn-4(Green): VIN-0 Driven By UNI-DAC-0.
VIN-0: High Limit=2.0V, Hysteresis=0V.
VIN-0 => 1.5V => 2.5V => Alert-0 Pin Asserted => UNI-DAC-0 Clamped(0V).
VIN-0 Jump High to Alert-0 Pin Asserted Period: 150uS.

JYI

Disable VIN-0 and IS-0 filters and repeating test got the different results.

VIN-0: 0V => 2.5V, Alert-0 Pin Asserted latency=4uS; 

VIN-0: 1.5V => 2.5V, Alert-0 Pin Asserted latency=5uS; and

IS-0: 0mA => 150mA, Alert-0 Pin Asserted latency=16uS.

Since the filter greatly effects the asserted latency (not sure this is correct), then in what situation, the filter should be turned on?

JYI

There is a little bit confused how to convert required voltage delta, such as 0.5V, to BI-VOUTx Hysteresis Register Code.  

Thanks.

JYI

Hi JYI,

concerning the filter, it is expected, that it affects the "response" to alert, as filtering acts as low pass. (Described at Datasheet Digital Filtering Section.) 

Function of the filter is to reduce "unwanted noise on dc signals", for such reason it should be used, when noise reduction is required by your system at ADC inputs.

Regards,

Arnost

Hi JYI,

concerning the " how to convert required voltage delta, such as 0.5V, to BI-VOUTx Hysteresis Register Code". It would be in principal similar as setting the limit code (asked previously at this thread). 

You can use following formula: 

Absolute range is determined by following table and in BI-VOUTx case is 10V:

Regards,

Arnost

Thanks.

Is it clear for Hysteresis settings 0xFFF0 or 0x7FF0 to keep Alert Pin not reset?

JYI

How to set target current, such as 10mA, to DAC Input register for close-loop mode?

JYI

Hi JYI,

Here is example, how to set target current in closed loop mode:

The closed loop works as a DAC to define the target current, represented as a voltage, VSET, between 0 V and 1.25 V (This is the value you are setting). A summing node to calculate the difference between the target current and the actual current. So if you wanted 10 mA the current sense voltage would be .01 * 5 = 0.05, multiplied by the gain of 6.25 = 0.3125. Divide that by full scale dac to get fraction = 0.3125/1.25 = 0.25. Multiply that by the full scale ADC code (2 ^ 12) = 1024 => 0x400. So writing 0x400 to the DAC register should set 10mA target current with a 5 ohm sense resistor.

Regards,

Arnost

PS: I apologize Alert Pin Reset is still under investigation.