Post Go back to editing

HIGH LIMIT 1 (PAGE 0x05) Registers Settings

Category: Datasheet/Specs
Product Number: AD7293

How to convert voltage range to HIGH LIMIT 1 (PAGE 0x05) registers settings for

AVDD, DAC Supply (DACVDD-UNI/DACVDD-BI) and AVSS High Limit Registers (Register 0x10 to Register 0x13),

BI-VOUT0MON to BI-VOUT3MON High Limit Registers (Register 0x14 to Register 0x17) and

RSx+MON High Limit Registers (Register 0x28 to Register 0x2B).

Vis verso, how to get their voltage reading from relative ADC conversion RESULT registers.

Thanks.

JYI

Parents Reply Children
  • Hi  ,

    maximum range of -7V is "maximum rating" to prevent destructive effect take place.

    GENERAL - POWER REQUIREMENTS table indicate AVSS to be in range of -5.5V to -4.5V (or 0V).

     

    DAC - DAC OUTPUT CHARACTERISTICS indicates DAC output voltages, where maximum negative output is -5V.

    Even when AVSS is -5.5V, maximum DAC output voltage is -5V.  

    Regards,

    Arnost

  • Is possible to keep Alert Summary and the corresponding alert registers not to be reset until a '1' is written to, even the alert condition is gone?

    Thanks.

    JYI

  • Hi  ,

    I am not certain if AD7293 will be able to perform exact functionality you are looking for, however I would suggest to explore possibilities of using "mask" registers and "alarm routing" to alert pins. 

    This might help you in your system application.

    Typically "Alert Summary" will be created and kept in the controller, by reading "all necessary" alert registers, when alarm is triggered. 

     

    Regards,

    Arnost

  • Thanks.

    The reason I asked this question is because the similar TI chip we have been used on our design has such functionality to allow host controller to get alert status even the alert condition is done.

    JYI

  • Hi JYI,

    Perhaps I haven't understood you question fully and what you are trying to achieve.

    Do you meant, that you want "alert" to be set once triggered, and to stay set even when "fault/out of limits" scenario is no longer present. In such configuration alert will stay set until manually cleared by the user. (by writing 1 to corresponding alert bit).

    Such functionality is available at AD7293, you can find it under hysteresis for alerts, program hysteresis to big enough value to corresponding alerts. Perhaps 4096 (full 12-bit range) in your case, and alerts once triggered will stay on, until manually cleared.

    Hope this helps. 

    Regards,

    Arnost 

  • Thanks for your response.

    The description scenario in your email is what I mean exactly.

    In our new design with AD7293, the alert pin is routing to sleeping pin to clamp the PA bias when the alert is triggered, such as bias current over driven. But once clamped, the bias current is down to zero, then the alert condition is gone, and the alert registers are reset. As the result, the host controller is unable to know what is happening even though it is noticed via alert signal, such as by interruption. 

    This is what I am looking for the solution for this scenario. I will try to use the way you suggested.

    JYI

  • Testing alert functionality on AD7293 EVAL Board according to your suggestion.

    Feeding UNI-DACx output to VINx and set VINx High Limit to 2V and VINx Hysteresis to 0xFFF (Register Read as xFFF0).

    Set UNI-DACx output to 2.5V -> VINx over High Limit -> Alertx Pin asserted (active LOW) -> UNI-DACx Output 0V (Clamped) -> Alertx Pin LOW last about 50-micro-second -> Alertx Pin deserted (idle HIGH) -> UNI-DACx Output Keeping 0V (Snooze Enabled).

    Alerte Summary and Alert Status Reset (Read Register 0x0000).

    This result is not what it should be as the one described on your response and is not what I expected.

    Is something missing?

    Thanks.

    JYI

  • Set Hysteresis x7FF (Register read back x7FF0), not xFFF keeps alert Pin and status registers un-reset even the alert "fault/out of limits" scenario is no longer present. Verified for VINx and BI-VOUTx, but failed to find such as description on data sheet. Not sure it is true for all alerts.

    JYI

  • Measurement of the period from the out of limit to alert pin asserted is about 300 micro-second with only one background channel enabled, such as VIN0. Increasing to two channels double this period.

    The ADC sample and conversion period should be less than 15-uS based on the data sheet. The 300-uS from alert condition triggering to alert pin assertion is normal for AD7293 or it can be shorter by the configuration.

    What is the fastest alert response timing for AD7293 for single monitoring channel? 

    Also, if snoozing disabled, the alert pin asserted period is much shorter than the deserted period. Should these two periods be the same based on ADC sample and conversion time.

    JYI