HIGH LIMIT 1 (PAGE 0x05) Registers Settings

Hi junboyi@bluedanube.com ,

thank you for your question, please refer to the AD7293 datasheet (DS), "Internal Channel Monitoring" section, which describes scaling of each of the mentioned channels. (Fugure 42. attached for your convenience, which reflects the same, more detaild description is in DS.) Resulting codes are then compared to determine, if ALERT will be triggered based on the configured limit. 

Regards,

Arnost

If I need to figure out how to map the input to Limit Register ADC data, then I don't need to ask questions here.

As user, I would like to have a simple, direct conversion between input voltage range to Mux range, especially for those with negative voltage range.

Thanks.

JYI

Hi junboyi@bluedanube.com, 

based on the input values indicated above, it is direct conversion using 12bit resolution. For example BI-Vout0MON have range -5V to 5V, this is scaled to 12bit resolution where -5V corresponds to 0x000 and 5V 0xFFF (as described in DS INTERNAL CHANNEL MONITORING section). 

Conversion for BI-Vout0MON can be done using this formula: LIMIT_CODE = ((Desired_Voltage_Limit+5)/10)*2^(12)) 

Here is described reasoning behind it: 

Similar approach needs to be taken for other inputs, here is direct equation examples:

RS0+MON:  LIMIT_CODE = ((Desired_Voltage_Limit)/62.5)*2^(12))

DACVDD-BI:  LIMIT_CODE = ((Desired_Voltage_Limit)/6.25)*2^(12))

DACVDD-UNI:  LIMIT_CODE = ((Desired_Voltage_Limit)/25)*2^(12))

AVSS:   LIMIT_CODE = ((Desired_Voltage_Limit+7.5)/10)*2^(12)) 

AVDD: LIMIT_CODE = ((Desired_Voltage_Limit)/6.25)*2^(12))

Regards,

Arnost

Very Usefully.

Thanks.

JYI

The section INTERNAL CHANNEL MONITORING of DS indicates there is a divider factor for each channel, such as for BI-Vout Mon, it says

For BI-VOUTxMON, divide by 8 and level shift within a −5 V to +5 V range, where 0x000
equates to approximately −5 V, and 0xFFF equates to approx-imately +5 V.

I wonder the above mapping formulas is including this divider factor or not.

For my understanding, the formulars is just for level shift, not including the input divider factor, right?

Thanks.

JYI

Hi junboyi@bluedanube.com ,

formulas indicated above shows conversion between input voltage and ADC code.

Scaling is happening internally on chip, and it is described in the datasheet mainly to give understanding concerning the input ranges, once input ranges are involved in the formula correctly it should account correctly for scaling and give you correct CODE output.

Input voltages are scaled to the value of 1.25V to be process by internal ADC, which have 1.25V voltage reference. 

I hope this helps to clarify you this topic. 

Regards,

Arnost

Thanks.

JYI

Is reset default setting for OFFSET 1 register good enough to use Internal Monitoring Functions or need to be setup for each monitoring channel?

Thanks.

JYI

Hi junboyi@bluedanube.com ,

OFFSET registers allows to eliminate unwanted the offset in your system. To determine, how precise internal measurement you need is dependent on your requirement and purpose of the internal monitors. Offset registers allows to adjust output value by range of 7 bits up and down (+128/-128 codes) out of 12bit resolution (4096 codes), which equals ~1/32 of full range. 

Out of the "box" accuracy of the AD7293 can be found the datasheet, in specification section (Table1).

Regards,

Arnost

Hi junboyi@bluedanube.com ,

OFFSET registers allows to eliminate unwanted the offset in your system. To determine, how precise internal measurement you need is dependent on your requirement and purpose of the internal monitors. Offset registers allows to adjust output value by range of 7 bits up and down (+128/-128 codes) out of 12bit resolution (4096 codes), which equals ~1/32 of full range. 

Out of the "box" accuracy of the AD7293 can be found the datasheet, in specification section (Table1).

Regards,

Arnost

Thanks.

I was confused with OFFSET-0 for DAC channel which needs to set offset for the output range.

JYI

The DS says AVSS maximum range -7V to +0.3V and BI-Vout is  AVss-0.3V to DACVdd-BI+0.3V.

Does the AD7293 be working when AVSS is less -5V, say -6.5V and have BI-Vout to be less than -5V, say -5.5 to -6V?  

Thanks.

JYI

Hi junboyi@bluedanube.com ,

maximum range of -7V is "maximum rating" to prevent destructive effect take place.

GENERAL - POWER REQUIREMENTS table indicate AVSS to be in range of -5.5V to -4.5V (or 0V).

DAC - DAC OUTPUT CHARACTERISTICS indicates DAC output voltages, where maximum negative output is -5V.

Even when AVSS is -5.5V, maximum DAC output voltage is -5V.  

Regards,

Arnost

I see.

Thanks.

JYI

Is possible to keep Alert Summary and the corresponding alert registers not to be reset until a '1' is written to, even the alert condition is gone?

Thanks.

JYI

Hi junboyi@bluedanube.com ,

I am not certain if AD7293 will be able to perform exact functionality you are looking for, however I would suggest to explore possibilities of using "mask" registers and "alarm routing" to alert pins. 

This might help you in your system application.

Typically "Alert Summary" will be created and kept in the controller, by reading "all necessary" alert registers, when alarm is triggered. 

Regards,

Arnost

Thanks.

The reason I asked this question is because the similar TI chip we have been used on our design has such functionality to allow host controller to get alert status even the alert condition is done.

JYI

Hi JYI,

Perhaps I haven't understood you question fully and what you are trying to achieve.

Do you meant, that you want "alert" to be set once triggered, and to stay set even when "fault/out of limits" scenario is no longer present. In such configuration alert will stay set until manually cleared by the user. (by writing 1 to corresponding alert bit).

Such functionality is available at AD7293, you can find it under hysteresis for alerts, program hysteresis to big enough value to corresponding alerts. Perhaps 4096 (full 12-bit range) in your case, and alerts once triggered will stay on, until manually cleared.

Hope this helps. 

Regards,

Arnost 

Thanks for your response.

The description scenario in your email is what I mean exactly.

In our new design with AD7293, the alert pin is routing to sleeping pin to clamp the PA bias when the alert is triggered, such as bias current over driven. But once clamped, the bias current is down to zero, then the alert condition is gone, and the alert registers are reset. As the result, the host controller is unable to know what is happening even though it is noticed via alert signal, such as by interruption. 

This is what I am looking for the solution for this scenario. I will try to use the way you suggested.

JYI

Testing alert functionality on AD7293 EVAL Board according to your suggestion.

Feeding UNI-DACx output to VINx and set VINx High Limit to 2V and VINx Hysteresis to 0xFFF (Register Read as xFFF0).

Set UNI-DACx output to 2.5V -> VINx over High Limit -> Alertx Pin asserted (active LOW) -> UNI-DACx Output 0V (Clamped) -> Alertx Pin LOW last about 50-micro-second -> Alertx Pin deserted (idle HIGH) -> UNI-DACx Output Keeping 0V (Snooze Enabled).

Alerte Summary and Alert Status Reset (Read Register 0x0000).

This result is not what it should be as the one described on your response and is not what I expected.

Is something missing?

Thanks.

JYI