Latch Enable Bias

Hi qrsc,

As long as the signal seen at the Latch-Enable inputs at the ADCMP572 side are within the specifications then it should be good.
It includes not only the input voltage levels but also the Setup time, Hold time and Minimum Pulse Width.

Check out the values at the Electrical Specifications table from the datasheet .

Best Regards,
Sham

It's unclear to me if the Latch Enable inputs are CML and whether I am allowed to ac-couple the signal.  The datasheet says the LE pins are internally terminated to VTT/VCCO and so I would assume it's OK to ac-couple since they bias internally.  But wanted to be 100% certain.  Also, does anyone know of an IBIS model exists for this device?

Hello,

Please refer to this statement in the Pin Functions Description on page 6 of the datasheet:


the LE/not LE inputs are differential inputs and therefore should always complement each other to function. The differential voltage should always be within the specs:

So, we can say that it is compatible to CML since the voltage swing is also 400mV and that the LE/notLE pins are also terminated to VCCO.

Please also refer to the timing diagram on page 13 of the datasheet to visualize the latch enable signal.

As for the IBIS model, we do not have one for ADCMP572, we only have one for ADCMP582 which is of the same family but different output logic (PECL). 


Best Regards,
Sham

Thanks.  Does the ADCMP582 have the identical input structure for the LE/LE* inputs as the ADCMP572?

Hi,

Yes, it does. 

Best Regards,
Sham

Thanks!