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Spice Model

Category: Hardware
Product Number: ADCMP605

Hi,

Is there a spice model for ADCMP605 or a similar comparator even if it is a single output version

Thanks,

Alan

  • Hello Alan,

    There is an available beta model for ADCMP604/605.
    Please send me your e-mail so I can give you a copy.

    Best Regards,
    Sham

  • Hello Sham,

    Thanks for your reply, my email address is

    alan.lawrenson@sony.com

    Many thanks,

    Best Regards,

    Alan

  • Hello Sham,
    please send me also the LT-Spice model.
    My address: eisenmann@hubert.de

  • Hello Sham,

       Could I get a copy of the ADCMP604 beta model as well, please?
    johann.crombach@unb.ca

    Thank you for your time,

    Johann

  • Hello everyone,

    I am posting the BETA model here for the benefit of all.
    Take note that this is just a BETA model.

    Best Regards,
    Sham


    * ADCMP604 SPICE Macro-model - BETA
    * Description: RR, 2.5 to 5.5V, SS, LVDS Comparator
    * Developed by: AR/ADGT
    * Revision History:
    * 1.0 (1/2021) - AR - BETA release
    * Copyright (c) 1998-2021 Analog Devices, Inc. All rights reserved.
    * Not Modeled:
    * Temperature effects
    * PSRR vs Frequency
    * CMRR vs Frequency
    *
    * Parameters modeled include:
    * VOS
    * IVR
    * Input Impedance
    * Active Gain
    * VOD
    * AC Performance
    * Supply Range and Current
    *
    * This is a BETA model only.
    * This is not the final model.
    *
    * Node Assignments
    * Q
    * | VEE
    * | | Vp
    * | | | Vn
    * | | | | VCCI/VCCO
    * | | | | | QB
    * | | | | | |
    .subckt ADCMP604 1 2 3 4 5 6
    B1 0 VDIN I=10u*dnlim(uplim(V(3),V(5)+.2,.1), V(2)-.5 ,.1)+1n*V(3)
    B2 VDIN 0 I=10u*dnlim(uplim(V(4),V(5)+.2,.1), V(2)-.5, .1)+1n*V(4)
    C1 VDIN 0 .5f Rpar=470k
    D5 0 VDH0 DLAT
    C4 4 2 1p Rpar=370k
    C10 3 2 1p Rpar=370k
    C7 5 1 200f
    C8 1 2 200f
    A6 N004 0 N002 0 0 0 VDH0 0 OTA g=500u linear Vlow=-1e308 Vhigh=1e308
    D6 0 N004 DLAT
    C3 N004 0 1p
    G1 0 N004 0 VDH0 500µ
    R4 N001 N003 14.5k
    A8 N001 2 0 0 0 N002 0 0 SCHMITT vt=.4 vh=0 trise=1n tfall=1.5n
    D1 VDIN 0 DVGAIN
    D3 N003 2 DBLE
    D2 5 4 DBIASR
    D4 4 2 DBIASF
    D7 5 3 DBIASR
    D8 3 2 DBIASF
    C15 5 6 200f
    C16 6 2 200f
    D10 5 2 DBURNSDI
    R1 5 2 19.2k
    D11 5 2 DBURNSDO
    D12 2 6 DESD
    D13 6 5 DESD
    D14 1 5 DESD
    D15 2 1 DESD
    D17 4 5 DESD
    D16 2 4 DESD
    D18 4 3 DBIASC
    D9 3 5 DESD
    D19 2 3 DESD
    R2 1 Vcm 10Meg
    R5 Vcm 6 10Meg
    M1 N010 N010 2 2 NPD
    M2 1 N010 2 2 NPD M=100
    B4 2 N010 I=(17.5u+1u*V(0))*(1-V(VDH))
    D22 2 N010 DLIM1
    M3 N008 N008 5 5 PPU
    M4 1 N008 5 5 PPU M=100
    B5 N008 5 I=(17.5u-1u*V(0))*(V(VDH)+1)
    D23 N008 5 DLIM1
    M5 N012 N012 2 2 NPD
    M6 6 N012 2 2 NPD M=100
    B6 2 N012 I=(17.5u+1u*V(0))*(V(VDH)+1)
    D24 2 N012 DLIM1
    M7 N011 N011 5 5 PPU
    M8 6 N011 5 5 PPU M=100
    B7 N011 5 I=(17.5u-1u*V(0))*(1-V(VDH))
    D25 N011 5 DLIM1
    C2 VDH0 0 40f
    B8 0 VDH0 I=100u*tanh(V(VDIN)/50m)*uplim(dnlim(100m*V(5,2)+1,1,.1),1.5,.1)
    A2 0 VDH0 0 0 0 0 VDH 0 OTA g=6.5m iout=5m Rout=1k Cout=700f vlow=-1 vhigh=1
    C9 VDH0 0 q=120f*dnlim(x,.7,.1)**1.5-100f*dnlim(-x,.7,.1)**1.5
    D26 VDIN 0 DVLIM
    C12 1 6 3p
    A3 2 Vcm 0 0 0 0 0 0 OTA g=100m iout=17.5u ref=-1.26 Rout=1Meg Cout=1f vlow=-1e308 vhigh=1e308
    C13 5 2 5p Rpar=83k
    C14 N001 2 1p Rpar=100
    I1 2 N001 12.52m
    S1 2 5 5 0 SVDDP
    .model SVDDP SW(level=2 Ron=10 Roff=100Meg vt=.5 vh=-.2 ilimit=10.36m)
    .model DVGAIN D(Ron=15k Roff=2Meg vfwd=15.3m epsilon=10m vrev=15.3m revepsilon=10m)
    .model DVLIM D(Ron=1k Roff=100Meg vfwd=60m epsilon=10m vrev=60m revepsilon=10m)
    .model DBLE D(Ron=31k Roff=1Meg vfwd=1.3 epsilon=100m)
    .model DLAT D(Ron=1 Roff=76k Vfwd=1 Vrev=1 epsilon=.9 revepsilon=.9)
    .model DBIASF D(Ron=300k Roff=1G vfwd=-400m epsilon=200m ilimit=2u )
    .model DBIASR D(Ron=80k Roff=1G vfwd=1 epsilon=150m ilimit=2u )
    .model DESD D(Ron=100 Roff=1G vfwd=650m epsilon=500m)
    .model DBURNSDI D(Ron=100 Roff=1Meg vfwd=1.6 epsilon=500m ilimit=500u)
    .model DBURNSDO D(Ron=100 Roff=1Meg vfwd=1.6 epsilon=500m ilimit=209u)
    .model DP D(Ron=1000 Roff=1Meg vfwd=1.6 epsilon=500m ilimit=20m)
    .model DBIASC D(Roff=100Meg Ron=750k vfwd=10u vrev=10u epsilon=10u revepsilon=10u ilimit=1u revilimit=1u)
    .model NPD VDMOS(kp=72.45u ksubthres=.1 vto=1)
    .model PPU VDMOS(kp=72.45u vto=-1 ksubthres=.1 pchan)
    .model DLIM1 D(Ron=100 Roff=1G vfwd=1 epsilon=500m)
    .model DSHT D(Ron=10k Roff=100Meg vfwd=2.2 epsilon=500m ilimit=.8u)
    .ends ADCMP604

  • Hello Sham,

    Thanks a lot for this spice model. When I try to run this in matlab, I am getting the following error:

    Function dnlim unrecognized.

    How can I resolve this?

  • Hello Uruj,

    It is most likely that matlab does not recognize the syntax.
    You must find the corresponding matlab syntax that will give you limiting or clamping function.


    Best Regards,
    Sham

  • Hi,

    I believe that the question has already been answered so I am closing this thread. Thank you!

    Regards,

    Paul

  • Hello! I want to bring to attention that the spice model for ADCMP604 available on the page https://www.analog.com/en/products/adcmp604.html#tools-header is not acurate. Instead the model available here is better. But again this is not compatible with other simulation programs like matlab or ADS