A few questions with respect to the ADP509x devices.
1. The ADP509x data sheet states in a couple of places that "for the best operation of the system, use PGOOD to enable the system load or to turn on an ultralow power load PFET". Exactly what performance benefit is achieved by using an additional external load switch?
2. If SYS or Reg_Out are enabled via an external load switch using PGOOD or REG_GOOD (5092 only), power to a connected load will experience a rather fast leading edge. Connected load capacitance will likely result in currents exceeding device limits, 1000 mA for SYS and only 150 mA for Reg_Out. Reg_Out is described as having an internal current limit of ~200 mA and SYS is stated as having no internal limit. It is further recommended to limit SYS and BAT currents to less than the 1000 mA spec. My questions are primarily associated with the Reg_Out piin as that is the pin I plan on using.
- Is the ADP5092 Reg_Out pin protected against high initial load capacitive in-rush currents, say 800 to 1000 mA by its internal current limit, or should some form of soft start be incorporated with an external load switch?
- Will high initial load capacitive in-rush effectively shut down the Reg_Out output? I.E. the data sheet states that the output voltage reduces to maintain a constant current limit. Will a high initial in rush current force the output into some sort of limit cycling that it can't get out of?
Thanks much for any clarification you can provide.