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Hi Friends,
I am interested in one of your high-speed dual-channel comparator AD96687 and I would like to use it in one of our projects.
We are not using the Latching function. so as per the datasheet, the Latch Enable pin should be Grounded Right?.
Even after completing the datasheet, I don't have a clear idea of the latching operation of the chip.
Can someone help me in solving this?

Parents
• Hi,

This comparator has differential latch mode input. These inputs must have different logical levels.

About disabling the latch function directly said:

Regards,

Kirill

In the above circuit, if the transistor Q4 is on, my output will be about 4.4V and if it is off my output will be 5V.
So my  ECL logic high means 5V (I am not sure) and my swing will be about 0.7V.

In the above circuit, if the transistor Q4 is on, my output will be about 4.4V and if it is off my output will be 5V.
So my  ECL logic high means 5V (I am not sure) and my swing will be about 0.7V.

Children
• If I understand you correctly, this is converter from non-ECL to ECL logic and you want use it for latch inputs driving?

• Yah, you got me.
Now my doubt is should I keep the Latch Enable pin at 5V because 5V is my ECL logic high state in order to disable the latching capability. But as per the datasheet, the maximum voltage at Latch Enable is -Vs to 0V.

• Classic ECL logic has a negative power supply of -5.2 volts. The logical element here is, in fact, a differential pair, one of the inputs of which is supplied with a reference voltage. This pair compares the input voltage with the reference voltage. The reference voltage here is minus 1.3 volts.

Once again pay attention to the logical levels

An input voltage higher than -1.3 volts is interpreted as logic 1. Ground voltage also is logic 1

Therefore, your converter must translate the input logic level below ground potential. Can you do that?

• Ok. I understood what you are saying.
But for my requirement, the ECL is switching between 5V and 4.4V and you can see it from my circuit provided.
My doubt is can I keep my Latch Enable pin at 5V to disable the latching operation?.

• Of course, exceeding absolute maximum ratings is a bad idea in itself. But I believe that you can use a voltage source of 5 volts but provided that you limit the current.

If it is said that the maximum current of the logic 1 is 40 μA, then ,in other words, this is quite enough to enable the function. Limit the current to about 40 µA using a resistor.

If you need to control the latch function, you need to lower the control input potential below the ground potential. If you only need to disable this function, you can use a pull-up resistor.

In the above circuit, I am using a 2 Channel Latching comparator AD96687.
I want the latching capability of comparator1 to be disabled, and comparator2 should be latched based on the output of comparator1. Is the circuit I provided apt for my requirement ?.

• Now I see that you only need to disable the latch function. But I have a few comments about your circuit.

To disable the latch function, it is enough to pull one of the corresponding inputs to the ground, why don't you use this? And if you want to pull it up to +5 volts, you need to limit the current flowing in. Applying a voltage higher than the ground potential to the logic input will cause a direct bias of the base-collector junction of the input transistor. This will result in a significant input current that may cause damage. And even if it does not cause damage, such a significant input current is not necessary for correct operation.

ECL logic has high-resistance pull-down resistors at the inputs, so it is acceptable to leave the inputs floating. It's good.

Do you use the output of the first comparator for control, but you don't use load resistors? The ECL logic outputs are an open collector, and pull-down resistors are required. This may work with internal resistors on the Latch Enable inputs, but you will not be able to take advantage of the high speed of this comparator.

If you connect these outputs to the inputs with as short wires as possible, you can avoid the complexities of designing microwave lines. But for a quick recharge of parasitic capacitances, the presence of load resistors at the outputs is mandatory.

If these resistors have a low resistance, say 50 or 75 ohms, it is advantageous to connect them to an additional power supply of -2 volts, to reduce the power dissipation. In your case, such low-value resistors are not required here, so it is possible to connect them to -5.2 volts directly. I would recommend a value of, say, 240 ohms.

Regards,

Kirill

• Thank you for your time.

I don't understand whether you mean one of the Latch Enable inputs or the Comparator inputs to be grounded to disable the latching operation.

In the datasheet, it is said that we need to ground the Latch Enable pin to disable the latching operation. The ground is the ECL logic high state.

I don't want to use the latching operation for my first compactor. So I connected the Latch Enable pin to +5V through a resistor since +5V is the logic high state and its complimentary pin is left to float. My ECL is swinging between +4.4V and +5V.

I want the second comparator to be latched based on the output of the first comparator.

I have found another chip ADCMP551BRQZ of Analog Devices with the same application and is PECL. Do you think this chip is more suitable for my purpose?.

• Hi Shibin,

Now this circuit seems much better to me. But you're talking about your ECL logic. Do I understand correctly that you want to use some special logic on discrete components and connect it to this comparator?

Because if you were using a standard ECL series, you wouldn't be asking these questions. This connects directly to each other.

First, please draw a more detailed circuit where these two parts are connected to each other:

Because I'm confused.

Thanks,

Kirill

• I don't understand whether you mean one of the Latch Enable inputs or the Comparator inputs to be grounded to disable the latching operation

The "lower floor" of the internal circuit of this comparator is the logical part. Here's what it looks like:

You can see that the logic input ground is interpreted as a logic level because the ground potential is higher than the Vr reference voltage. I hope this will clarify something for you

The positive supply voltage is used by the analog comparator circuit itself. I understand this intuitively. Unfortunately, the Analog Devices application engineers don't participate in this discussion and can't tell if I'm right or wrong.