For all the evaluation kits (MAXM86161EVKIT/SYS, MAXM86146EVKIT/SYS, MAX86176EVSYS, MAX86171EVSYS, MAX86140/1EVSYS)
that contain the MAXSENSORBLE_EVKIT board, the timestamp format and how timestamps are generated is explained in the following summary:
Format
The timestamps are in milliseconds (ms) from the epoch (converter).
Generation
FW logic:
- SW sends wall clock time
- SW sends start command (enables RTC and sensors)
- Delay before ADC starts (i.e., MAX86141 DAC cal = ~180ms, other sensors = ~20ms)
- FIFO data is read periodically
- Every ~1s the RTC value is saved (RTC is read on FIFO interrupt)
- SW sends stop command
- The final RTC value is sent with the last FIFO sample(s)
- SW sends wall clock stop time (unless the device loses power before SW can send it)
Parser logic:
- If a start and stop wall clock timestamp are available:
- The RTC tick period is: (start - stop - delay)/ (final RTC value)
- The default delay is 180ms for MAX8614x, 20ms for other sensors, but is adjustable via a parser parameter
- The RTC tick period is: (start - stop - delay)/ (final RTC value)
- Otherwise:
- The RTC tick period is (RTCscale +1)/32.768kHz
- Default RTCscale = 31
- The RTC tick period is (RTCscale +1)/32.768kHz
- The number of samples between two successive RTC values (which is saved every ~1s) gives the sample period for that group of samples
- The group of samples before the first RTC value uses (start – delay)/(number of samples before first RTC value). Hence if the delay is way off the mark, the sample period for this group will also be.
- It’s best to ignore the sample period for this group of samples
- If there isn’t a wall clock stop time (due to power loss), then the last group of samples will not have a sample period
- Each sample’s timestamp is the previous sample’s timestamp + its group sample period
- The first sample’s time stamp is the wall clock timestamp + its group sample period