There are two kinds of interrupt sources relevant for reading data from the MAX30101 or MAX30102.
The first is A_FULL, which triggers when the 32 samples of FIFO data is about to get full. The number of free samples away from full FIFO can be programmed by setting FIFO_A_FULL[3:0] in the FIFO Configuration register. For example, the interrupt can be triggered when the FIFO is one sample away from being full, or when it is two samples away from being full. The interrupt is cleared by reading the Interrupt Status 1 register (0x00). If A_FULL_EN is set, the master will be informed to read the data via hardware interrupt once the interrupt triggers. Otherwise, the host will have to poll the Interrupt Status 1 register to determine whether the interrupt has occurred.
The second is PPG_RDY, which triggers for every new sample of data. The interrupt is cleared by reading the Interrupt Status 1 register (0x00), or by reading the FIFO_DATA register. If PPG_RDY_EN is set, the host processor will be informed to read the data via hardware interrupt once the interrupt triggers. Otherwise, the host will have to poll the Interrupt Status 1 register to determine whether the interrupt has occurred.