ADPD107 External sampling sync trigger

Hello,

I received a question about sync trigger of ADPD107 from our customer.

The customer input a trigger signal (25Hz) to GPIO0. And he checked PDC timing. But the PDC timing has variation around +/-1usec as the trigger signal.  Is this ADPD107's specification? Or can we improve the variation?

Best regards,

Akira

  • 0
    •  Analog Employees 
    on Jul 24, 2018 12:35 AM

    Hello,

    I'm not sure exactly what timing you're referring to. If they are using an external sync, then that will trigger the state machine to initiate a new sample. The PDC pin is a cathode voltage, so when you refer to "PDC timing", it's a bit confusing. The AFE timing, which is the timing of LED pulses and integration sequences is controlled by the on-chip 32MHz oscillator. This is a different clock domain than the state machine clock so it is entirely likely that if you are trying to measure time differences between two different clock domains that you will see variations from sample to sample. We do not have a maximum spec on this.

    The question I have is why is a +/- 1us delta important when measuring a heart beat that occurs on the order of once every second?

    Regards,

    Kevin

  • Hi Kevin,

    Thank you for your support.

    Thanks & Regards,

    Akira