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EVAL-ADPD4100Z-PPG ground pattern

Category: Hardware
Product Number: ADPD4100

I'm a DFAE in Japan.

My customer asked me why EVAL-ADPD4100Z-PPG have slit patters in layer2 ground and layer5 ground(attached)

Please let me know the purpose of the slit patterns.

  • Hi,

    The layer-2 ground and layer-5 ground of the EVAL-ADPD4100Z-PPG board are actually connected together. The purpose to have two layers of ground is to shield layer-3 power and layer-4 signal from the top layer that has most of the components and the bottom layer that has the LEDs and PDs.

    There are 3 sensitive nets we take care of most, 1) PD-Cathode 2) PD-Anode 3) ADC_VREF.  Noise injected on any of these nodes can show up in the data.  It is important to not allow clocking signals to be adjacent to a sensitive net.  We will try to position ground planes around these nets and sometimes under them to ensure that other clocking signals do not couple in.

    VLED and VDD1 can be “noisy” supplies.  These are OK shields for the digital lines but are not ideal shields for the 3 sensitive nets.  In the layout, we may stretch out the ground lines to ensure that they shield the sensitive nets.