I'm having a problem with simulating LTC6563 in LTSpice. Two issues that I found:
When I measure bandwidth in LTSpice, the -3dB cutoff is around 110 MHz, whereas charts in the datasheet (page 12) are showing that it should be ~500 MHz or less depending on input capacitance. I try to simulate the input source, with a current source and with a voltage source with a resistor (as shown in figure 1 in the datasheet) but the results are roughly the same. In the attached you can find LTSpice file with both of approaches.
2. Offset input bandwidth limitation.
In My application, I want to change offset "on the fly" during My measurement, so I was trying to determine the frequency limitation of this solution. The datasheet is stating "Offset Voltage to Output Settling" as 100ns so I was assuming the cut-off is around 3.5MHz. In the attached, you can find LTSpice file of My approach to test this solution. I1_2 and V9 are set so that they cancel each other and there is no signal on the output. My understanding was that I will change the frequency in both sources and at some point, the BW limitation of the offset pin will start to rise and I will see some signal on the output. But no matter what frequency I put in there is no signal at the output, It looks like there is no BW limitation simulated on the offset pin.
Is there some mistake in My approach to testing things ? Any help will be appreciated.