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About ADPD105/108 calibrating the 32 MHz clock

Hi

According to datasheet page 33 "calibrating the 32 MHz clock".


If the CLK_RATIO more than 2000, the clock error value will be a negative number


1. In this situation how did I set the CLK32M_ADJUST(0x4D) ?

2. CLK_RATIO value will change everytime , how did I deter the setting value of CLK32M_ADJUST?